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Posted By: neyha Member Level: Diamond Posted Date: 07 May 2008
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2006 Anna University Electronics and Communication B.E./B.TECH.DEGREE EXAMINATION:COMPUTER ARCHITECTURE Question paper
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B.E./B.TECH.DEGREE EXAMINATION, MAY/JUNE 2006
IV -SEMESTER
COMPUTER ARCHITECTURE
TIME : 3 HRS
MAX MARKS : 100
PART - A (10 X 2 = 20 MARKS)
1. Give an example each of zerro address, one-address, two-address and three-address instructions
2. Which data structure can best be supported using (a_indirct addressing mode (b) indexed addressing mode?
3. What is the purpose of guard bits used in floating point operations?
4. Give the booth's recoding and bit pair recoding of the number 1000111101000101.
5. Why is the wait-for -memory-function-completed step needed when reading from or writing to the main memory?
6. How do control instructions like branh cause problems in a piplined processor?
7. What is the function of a TLB (translation look aside buffer)?
8. An eigth way associative cache consists of atotal of 256 blocks. The main memory contains 8192 blocks,each consisting of 128 words.
(a) How many bits are there in the main memory address?
(b) How many bits are there in the TAG,SET and WORD fields?
9. Why are interupt masks providd in any processor?
10 How does bus arbitration typically work?
PART- B
11(i) Explain in detail the different types of instructions that are supported in a typical processor.
(ii) Registers R1 and R2 of a computer contains decimal value 1200 and 2400 respectivily. What is the effective address of the memory operand in each of the following instructions?
(i) Load 20 (R1),R5
(2) Add -(R20) ,R5
(3) Move #3000,R5
(4) Sub (R1)+,R5
12(a) Explain in detail the principle of carry-look-ahead adder .Show how 16 bit CLAs can be constructed from 4 bit adders
(ii) Perform the division on the follwing 5-bit unsigned integer useing non-rstoring division 10101/00101
OR
(b) (i) Explain the working of a floating point adder /suntractor
(ii) Multiply the following pair of signed 2's complement numbers using bit pair recoding of the multipliers :A = 010111,B = 101100
13 (a) (i) Explain how pipelinning helps to speed up the processor . Discuss the hazards that have to be taken care of in a pipe lined processor.
(ii) Give the sequence of control signals to be generated to fetch an instruction from memory in asingle bus organization.
OR
(b) Explain in detail the working of micro-programmed control unit.
14 (a) (i) Discuss the address translation mechanism and the different pages replacement policies used in a virtual memory system
(ii) A byte-addressable computer has small data cache capable of holding eigth 32 bit words. Each cache block contains one 32 - it word. When a given program is exacuted ,the processor reads data from the following sequence of hex address-
200,204,208,20C,2F4,200,204,218,21C,24C,2F2. The pattern is repeated 4 times. Assuming that the cache is initially empty, show the contents of the cache at the end of each pass, and compue the hit rate for a direct mapped cache.
OR
(b) (i) Discuss the various mapping schemes used in cache design. Compare the schemes in terms of cost and performance.
(ii) Consider a two level cache with acess time of 5ns, and 80 ns respectivily. If the hit rates are 95%, and 75% respectivily in the two caches , and the memory acess time is 250 ns , what is the average access time?
15 (a) (i) Explain the use of vectored interrupts in processors . Why is priority handling desired in interrupt controllers ? How do the different priporiy schemes work?
(ii) Discuss the data transfer mechanism of the PCI bus.
OR
(b) (i) Explain how data may be transferred frm a hard disk to memory using DMA including arbitration for the bus . Assume a synchronous bus and draw the timming diagram showing data transfer.
(ii) Discuss the salient feature of the USB operation
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