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Posted By: palaniappan Member Level: Silver Posted Date: 13 May 2008
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2004 Anna University B.E Computer Science COMPUTER ARCHITECTURE -II Question paper
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2004 Anna University B.E Computer Science CS340- COMPUTER ARCHITECTURE -II Question paper
Course: B.E Computer Science University: Anna University
H309
BE/B.TECH DEGREE EXAMINATION, APRIL/MAY 2004
Sixth Semester
Computer Science and Engineering
CS340- COMPUTER ARCHITECTURE -II
Time:3hrs Maximum:100marks
Answer ALL questions.
PART A-(10X2=20 marks)
1.What are the problems with using MIPS as a measure of performance of a computer?
2.What are the various optimizations performed by modern compilers?
3.What are Pipleline Latches?
4.State the principle of simplest scheme to handle branches in piplelining.
5.List out the possible operations specified in VLIW instruction.
6.Based on what factors,the vector execution time will be calculated?
7.Show the basic structure of a centralized shared memory multiprocessor.
8.What are cache coherence protocols?Give an example.
9.Mention the advantages of Register windows in RISC architecture.
10.List out the properties of Data flow machines.
PART B-(5X16=80 marks)
11.(i)Discuss about the various issues and parameters involved in the performance analysis of a computer.(10)
(ii)Bring out the advantages and disadvantages of the three common types of general purpose register machines.(6)
12.(a)(i)Show that the pipleline stalls will degrade the performance of the system.(6)
(ii)Discuss about control Hazards in pipelined system.(10)
Or
(b)(i)Describe the difference level of parallelism used?(8)
(ii)Explain the dynamic scheduling and dynamic hardware branch prediction.(8)
13.(a)(i)Explain the limitations of multiple issue processors.(6)
(ii)Explain the architecture and function of super scalar processor.(10)
Or
(b)Show the architecture of a vector processor.Explain the function of load store units and vector memory
access schemes.(16)
14.(a)Discuss about the structure of a distributed shared memory system with various interconnection schemes
and message passing mechanisms.(16)
Or
(b)(i)Explain the need for synchronization in multiprocessors.(6)
(ii)Describe the schemes for enforcing coherence in multiprocessors.(10)
15.(a)(i)Describe the parameters to be considered for bus design.(6)
(ii)Explain the bus interconnection structure and characteristics of SCSI bus shared.(10)
Or
(b)(i)Explain what are stack processors.(4)
(ii)Explain the architecture ,instructions and addressing modes of a RISC processor.(12)
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