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Posted By: palaniappan Member Level: Silver Posted Date: 14 May 2008
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2008 Anna University B.E Computer Science Computer Architecture Univarsity questions Unit - IV Question paper
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CS1251 – Computer Architecture
Question Bank
Unit – IV
Note : All the following questions are from the past university exam question papers.
Part - A
1. What is the function of TLB?
2. An eight way set associative cache consists of a total of 256 blocks. The main memory contains 8192 blocks, each consisting of 128 words.
a. How many bits are there in the main memory address?
b. How many bits are there in TAG, SET and WORD fields?
3. What do you understand by Hit Ratio?
4. Define locality of reference? What are its types?
5. Distinguish between write-through and write-back policies pointing out their relative merits and demerits
6. Write down the expression for the average memory access time for a system with three levels of caches with hit ratios h1, h2, h3 and the access times tc1, tc2, tc3 and main memory access time tm. Explain the same.
7. An eight way set associative cache consists of a total of 256 blocks. The main memory contains 8192 blocks, each consisting of 128 words.
a. How many bits are there in the main memory address?
b. How many bits are there in TAG, SET and WORD fields?
8. What is virtual memory? How is it implemented?
9. What will be the width of address and data buses for a 512Kx 8 memory chip?
10. List the factors that determine the storage device performance.
11. How many 128 x 8 RAM chips are needed to provide a memory capacity of 2048 bytes?
12. Draw the memory hierarchy diagram and mention about size, cost and speed of operation of each block.
13. What is an interleaved memory system? Discuss
14. What is meant by memory interleaving? Show the distribution of addresses for a memory system consisting of two banks of four 1K memory modules to form an 8K memory system. Give the main memory address format.
15. What is parallel processing?
16. What is the necessary for virtual memory?
Part – B
1. Draw a neat sketch of memory hierarchy and explain the need of cache memory. (8)
2. Discuss the various mapping functions used for mapping main memory blocks into cache memory. Compare the schemes in terms of cost and performance (10)
3. Consider a two level cache with access time of 5ns and 80 ns respectively. If the hit rates are 95% and 75% respectively in the two caches and the memory access time is 250ns, what is the average access time? (6)
4. Explain the virtual memory address translation and TLB with necessary diagram. (10)
5. Discuss the concept of memory interleaving and give its advantages. (6)
6. Write notes on static memories. (8)
7. Explain the concept of memory hierarchy. (8)
8. Write notes on (i) ROM technologies.
(ii) Memory interleaving.
(iii)Set Associative mapping of cache.
(iv)RAID Disk arrays (16)
9. What is virtual memory? Explain how the logical address is translated into physical address in the virtual memory system with a neat diagram. (10)
10. Describe the organization of a typical RAM chip. (6)
11. Explain the organization of magnetic disk in detail. (6)
12. A digital computer has a memory unit of 64 K x 16 and a cache memory of 1K words. The cache uses direct mapping with a block size of four words. How many bits are there in the tag, index, block and word fields of the address format? How many blocks can the cache accommodate? (10)
13. A computer system has main memory consisting of 1M 16 bit words. It also has a 4K word cache organized in the block set-associative manner, with 4 blocks per set and 64 words per block. Calculate the number of bits in each of the TAG, SET and WORD fields of the main memory address format. (6)
14. Consider a main memory of size 128 MB and a cache of size 64kB. If the block size is 64 bytes and cache uses 4-way-set-associative mapping, give the main memory address format and explain. (6)
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