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Posted By: Sri Member Level: Gold Posted Date: 14 Dec 2007
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2006 Jawaharlal Nehru Technological University B.Tech Electrical and Electronics Engineering III/Sem1 Regular (NOV)Set 4,Computer Organization Question paper
Code No: RR310201 Set No. 4
III B.Tech I Semester Regular Examinations, November 2006
COMPUTER ORGANIZATION
( Common to Electrical & Electronic Engineering, Electronics &
Communication Engineering, Electronics & Instrumentation Engineering,
Electronics & Telematics and Instrumentation & Control Engineering)
Time: 3 hours Max Marks: 80
Answer any FIVE Questions
All Questions carry equal marks
1. Describe all optional PCI signal lines with designation and type. [16]
2. Write an algorithm to add binary numbers represented in normalized floating point
mode with base 2 for exponent. [16]
3. (a) Discuss various aspects of instruction set design.
(b) Explain about various types of data on which machine instructions operate.
[10+6]
4. (a) Differentiate between large register file versus cache.
(b) Discuss how compiler based register optimization is done.
(c) Explain various characteristics of reduced instruction set architectures.
[6+6+4]
5. (a) Differentiate between single versus two-level caches.
(b) Elaborate on Pentium Cache Organization. [8+8]
6. (a) What is ‘data striping’ ?
(b) Discuss about the recent disk system developments.
(c) Explain the control command operations enabled by magnetic tape drive controller. Also explain about cartridge tape system. [4+4+8]
7. (a) Discuss about I/O channel architecture.
(b) Discuss about I/O addressing in 8086.
(c) Discuss the salient features of laser printer [6+6+4]
8. (a) Give a summary of arithmetic and logical operations that are defined for the
vector architecture.
(b) What is cache coherence problem. Discuss about different cache coherence
approaches. [8+8]
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