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Posted By: Sra1       Member Level: Diamond       Posted Date: 27 May 2008

2007 Jawaharlal Nehru Technological University B.Tech Mechanical Engineering ELECTRONIC DEVICES AND CIRCUITS (Supplimentary Examinations, Aug/Sep 2007) Question paper



Course: B.Tech Mechanical Engineering   University: Jawaharlal Nehru Technological University




Set No 1
-------------
Time: 3 hours Max Marks: 80
Answer any FIVE Questions
All Questions carry equal marks

1. (a) Explain about Drift and Diffusion currents in semiconductors. [3+3]
(b) Explain about cut-in voltage of forward characteristic of semiconductor diode
[4]
(c) Calculate the magnitude of maximum electric field at 3000K for P-N junction
with NA=1020 /cm3 on P-side and ND=1015 /cm3 on N-side of a Silicon semi-
conductor diode.Intrinsic carrier concentration ni =2.5x1010/cm3 and. VT=25
mv at 3000K [3]
(d) Explain about the significance of built-in voltage [3]
2. (a) Discuss the method of conversion of ac voltage into unidirectional voltage
using a semiconductor diode.
(b) Draw the input signal and output signal waveforms of a Full wave rectifier
circuit
(c) Derive the expressions for VD.C and VR.M.S for a full wave rectifier circuit.
(d) Derive the expression for ripple factor of a Full wave rectifier circuit.
[3+3+4+6]
3. (a) Draw a diagram showing Various currents in a PNP Transistor in CB mode.
(b) Explain the phenomenon of Base width modulation in Transistor operation
and discuss its influence on Base current ‘IB’ in a Common Base operated
Transistor.
(c) Draw the output characteristics of a Common Base operated Transistor and
discuss the role of ‘Early Effect’ on the CB Transistor output characteristics.
(d) Explain the operation of a PNP Transistor in Common Base configuration.
[3+3+4+6]
4. (a) Draw the circuit diagrams showing the three configurations of Transistor am-
plifiers.
(b) Draw the Transistor biasing circuit using Collector-to-base bias arrangement.
Explain the concept of providing proper bias for the Transistor to act as am-
plifying device
(c) Mention the DC load line equation for CE Transistor Collector to base bias
circuit and describe the method of drawing the DC load line on the CE Tran-
sistor output characteristics. [6+6+4]
5. (a) Draw the practical circuit of a single stage Common Base Transistor Amplifier
with potential divider biasing.
(b) Assuming sinusoidal input signal to the above CB Transistor amplifier, explain
the working of the amplifier with necessary waveforms.
(c) Draw the A C equivalent circuit of the CB Transistor amplifier and explain
the concept of amplification and mention some practical applications of it.
[4+4+8]
6. (a) Draw the potential divider bias circuit for P-Channel JFET and explain the
function of each component in the circuit.
(b) Derive the expression for voltage gain of JFET model for self bias configura-
tion. [8+8]
7. (a) Explain the effects on
i. Noise
ii. Nonlinear distortion and
iii. Bandwidth of amplifiers with the introduction of voltage series feedback
into the amplifiers
(b) An amplifier with an open-loop voltage gain AV of -1000 delivers 10 watts
of output power at 10% second harmonic distortion, when the input signal
is 10mv. If 40 db negative voltage-series feedback is applied and the output
power is to remain at 10 watts; calculate
i. the required input signal
ii. percentage second harmonic distortion and
iii. Closed-loop voltage gain. [8+8]
8. (a) What are the limitations of RC phase shift oscillators? How do you overcome
them?
(b) Draw a typical practical version of a FET Colpitts oscillator circuit and explain
its working.
(c) Mention the expression for the calculation of Colpitts oscillator circuit fre-
quency. If the colpitts oscillator frequency is 2.2 MHZ and the inductance L
= 0.2 mH; calculate the value of the equivalent capacitor ‘Ceq’ in the frequency determining network. [4+8+4]





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