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Posted By: Sra1 Member Level: Diamond Posted Date: 27 May 2008
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2007 Jawaharlal Nehru Technological University B.Tech Mechanical Engineering ELECTRONIC DEVICES AND CIRCUITS (Supplimentary Examinations, Aug/Sep 2007) Question paper
Set No 4
---------------
Time: 3 hours Max Marks: 80
Answer any FIVE Questions
All Questions carry equal marks
? ? ? ? ?
1. (a) Discuss the significance of Forbidden Band Gap energy in Energy-Band Dia-
grams with reference to the difference in cut-in voltages for Silicon and Ger-
manium diode working under forward Bias conditions.
(b) Mention the reason for Silicon devices to work at higher temperatures when
compared to Germanium devices with necessary Energy Band diagrams.
(c) Calculate the magnitude of barrier voltage at 3000K for P-N junction with
NA=1018/cm3 on P-side and ND= 1015/cm3 on N-side of a Germanium semi-
conductor diode. Intrinsic carrier concentration ni= 1.5x106/cm3 and. VT=25
mv at 3000K. [6+6+4]
2. (a) Discuss the functioning of rectifier circuits in DC sources for Electronic cir-
cuits.
(b) Draw the circuit diagram of FullWave rectifier using two semiconductor diodes
and explain its working principle.
(c) Mention the expression for rectification efficiency
(d) Derive the expression for rectification efficiency [3+7+3+3]
3. (a) Draw a diagram showing Various currents in a PNP Transistor in CB mode.
(b) Explain the phenomenon of Base width modulation in Transistor operation
and discuss its influence on Base current ‘IB’ in a Common Base operated
Transistor.
(c) Draw the output characteristics of a Common Base operated Transistor and
discuss the role of ‘Early Effect’ on the CB Transistor output characteristics.
(d) Explain the operation of a PNP Transistor in Common Base configuration.
[3+3+4+6]
4. (a) Why biasing is necessary for a Transistor circuit in a given configuration.
Mention the three different types of biasing a Bipolar Junction Transistor.
(b) Draw the Transistor biasing circuit using fixed bias arrangement and explain
its principle with suitable analysis.
(c) Mention the DC load line equation for CE Transistor fixed bias circuit and
describe the method of drawing the DC load line on the CE Transistor output
characteristics. [6+6+4]
5. (a) Discuss the four basic methods of coupling for cascading of amplifiers to obtain
Multi-Stage amplifiers and mention the reasons for cascading of amplifiers.
(b) Draw a typical block diagram of 3-stage CE Cascaded amplifier.
(c) Derive the expressions for voltage gain and the resultant phase shift of cas-
caded amplifier of these 3-stages. [6+4+6]
6. (a) Draw fixed biasing circuit of N-Channel FET and explain the function of
each component in the circuit in fixing the quiescent operating conditions of
amplifiers.
(b) Explain the action of JFET amplifier using fixed biasing scheme. [8+8]
7. (a) Discuss the merits and demerits of negative and positive feedback amplifiers
(b) It is required to have an amplifier with a closed loop gain AV f = -100 and a
gain which should not vary by more than 1%, when the non-feedback amplifier
gain varies by 20%. Compute the values of
i. AV and
ii. ß
[4+12]
8. (a) Draw the circuit of R-C phase shift oscillator circuit using JFET as the active
device and discuss the nature of feed back used in the feedback path.
(b) In the R-C phase shift oscillator circuit, discuss the passive of part of the
circuit that is responsible to get the 1800 phase shift.
(c) Calculate the value of ‘C’ in the frequency-determining network of a FET ?
RC phase shift oscillator circuit having R = 2.5 K ; assuming frequency of oscillation f = 1.625 KHZ.
(d) Repeat (c) if it is a BJT ? RC phase shift oscillator with RC = 4k [5+5+3+3]
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