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Posted By: ashish Member Level: Diamond Posted Date: 20 Dec 2007
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2005 Indira Gandhi National Open University (IGNOU) M.C.A COMPUTER ORGANISATION & ASSEMBLY LANGUAGE PROGRAMMING 2005 Question paper
MCS-012 : COMPUTER ORGANISATION & ASSEMBLY LANGUAGE PROGRAMMING
DECEMBER, 2005
Time: 3 hours
Maximum Marks: 100
(Weightage 75%)
Note : Question number 1 is compulsory and carries 40 marks. Answer any three questions from the rest.
1. (a) Perform the following arithmetic operations using 8-bit registers utilising signed 2's complement representation. Indicate the overflow, if any. (5)
(i) 75 + 53
(ii) (- 75) - 53
(iii) (- 53) - (- 13)
(iv) 53 + (- 13)
(b) A digital computer has a memory unit of 64 K x 16 and a cache memory of 1 K words. The cache uses direct mapping with a block size of four words.
(i) How many bits are there in the tag, index, block and word fields of the address format ?
(ii) How many bits are there in each word of cache, and how are they divided ? Include a valid bit.
(iii) How many block can the cache accommodate ? Draw suitable diagrams, wherever needed. (7)
(c) What is an assembler ? How does a two pass assembler work ? (3)
(d) A 36-bit floating point binary number has eight bits plus sign bit for the exponent and 26 bits plus sign bit for mantissa. The mantissa is a normalized fraction. Assume signed magnitude representation for numbers. What are the largest and smallest positive and negative values excluding zero that can be represented using this representation ? Make suitable assumptions, if any. (5)
(e) What is a micro-operation ? How is it different from an instruction of a computer ? Explain the steps of 'instruction fetch' and 'interrupt processing'. (8)
(f) Starting from an initial value of R = 11011011, determine the sequence of binary values in R after a logical shift-left, followed by a circular shift-right, followed by a logical shift right, followed by a circular shift left and an arithmetic shift right operations are performed on the register. Show the value after each operation. (3)
(g) Write a progam in 8086 assembly language to add two single-digit ASCII numbers, stored in CL and BL registers. The result should be in AX register (AL having the value and AH having the carry bit). (4)
(h) Simplify the following expression in SOP form using a K-map. (5)
F(A, B, C, D)- ABar + BC - ABar DBar
2. (a) Design a 2 bit count-down counter. This is a sequential circuit with 2 flip-flops and one input x. The state sequence for this counter is
11, 10, 01, 00, 11. (10)
(b) In RAID levels, explain the features of those levels which have excellent read request rate. (5)
(c) Write a program in assembly language for finding the smallest and largest number in a given set of numbers. (5)
3. (a) Construct a 5-to-32 line decoder using four 3-to-8 line decoders with enable and one 2-to-4 line decoder. (5)
(b) What is associative memory ? Explain the concept of Match-logic for associative memories. (5)
(c) What is FAT ? Calculate the number of entries required in the FAT table, using the following parameters for an MS-DOS system : (5)
Disk capacity - 30 MB
Block size - 1024 bytes
Blocks/Clusters - 4
(d) Explain the working of three way instruction pipelining in a RISC system. What are the limitations of this pipeline ? (5)
4. (a) Construct and explain the block diagram for a 2 bit adder-subtractor circuit. (5)
(b) Explain the memory interleaving technique with the help of a diagram. (5)
(c) Explain the working of CD-ROM and DVD ROM. (5)
(d) Explain the working of the Wilkes Control Unit. (5)
5. (a) Explain the internal architecture of a DRAM that stores 4 K bytes chip size and uses a square register army. How many address lines will be needed ? Suppose the same configuration exists for an old RAM, then how many address lines will be needed ? (10)
(b) What is the difference between direct and indirect address instructions ? How many memory references are required for each type of instruction to bring an operand into a processor register ? Explain this. (5)
(c) Find the length of a SEC code and a SEC-DED code for a 16-bit word data transfer. (5)
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