My Profile
Active Members
TodayLast 7 Days
more...
Awards & Gifts
Online Exams
Fresher Jobs
Our fresher job section is exclusively for fresh graduates! Find jobs for freshers in major Indian
cities including Bangalore, Chennai, Hyderabad, Pune or Kochi
Resources
Find educational articles, blogs, discussion threads and other resources.
Colleges
Find details about any college in India or search for courses.
|
Download Model question papers & previous years question papers
|
Posted By: neyha Member Level: Diamond Posted Date: 12 Jun 2008
|
2007 Anna University Electronics and Communication B.E / B.Tech. DEGREE EXAMINATION: VLSI DESIGN Question paper
|
|
|
B.E / B.Tech. DEGREE EXAMINATION,NOV/DEC 2007
VLSI DESIGN
VII SEMESTER
Time : 3 Hrs
Max Marks : 100
PART A (10 X 2 = 20 )
1. What are the advantages of SOI CMOS process?
2. Distinguish electically alterable and non- electricall alterable ROM.
3. Compare nMOS and pMOS devices.
4. Compare enhancement and depletion mode devices
5. What is meant by coninous assignments in verilog HDL?
6. What is a task in Verilog ?
7. Give the applications of PLA
8. What is meant by transmission gate?
9. What is the aim of adhoc test techiques?
10 Distinguish functionality test and manufacturing test.
PART -B (5 X 16 =80)
11. (a) (i0 Draw and explain the n-well process
(ii) Explain the twin tub process with a neat diagram
OR
(b) (i) Discuss the origin of latch up problems in CMOS circuits with necessary diagrams . Explain the remedial measures
(ii) Draw and explain briefly the n-well CMOS design rules
12 (a) (i) Derive the expression for the drain - to - source current in the nonsaturated and the saturated rgeions of operation of an nMOS transistor
(ii) Define and derive the transconductance of nMOS transistor
OR
(b) (i) Discuss the small signal model of an MOS transistor
(ii) Explain the CMOS inverter DC charecteristics
13 (a) (i) Give a verilog structural gate level description of a bit comparator.
(ii) Give a brief account of timming control and delay in verilog
OR
(b) (i) Give a Verilog structural gate level description of a ripple carry adder
(ii) Write a brief note on the conditional statements available in verilog
14(a) (i) Compare the different types of ASIC's
(ii) Discuss the operations of a CMOS latch
OR
(b) Explain the ASIC design flow wiht a neat diagram . Enumerate clearly the different steps involved
15 (a) Explain the chip level test tescniques
OR
(b) Explain the system level test techniques
Return to question paper search
|
|
|
Submit Previous Years University Question Papers and make money from adsense revenue sharing program
Are you preparing for a university examination? Download model question papers
and practise before you write the exam.
|
Watch TV Channels
|