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Posted By: Sree....       Member Level: Diamond       Posted Date: 15 Jun 2008

2006 Andhra Pradesh State Jawaharlal Nehru Technological University B.Tech VLSI SYSTEMS DESIGN Set No.4 Question paper



Course: B.Tech   University: Jawaharlal Nehru Technological University




Code No: RR410505 Set No. 4
IV B.Tech I Semester Supplementary Examinations, March 2006
VLSI SYSTEMS DESIGN
( Common to Computer Science & Engineering, Computer Science &
Systems Engineering and Electronics & Computer Engineering)
Time: 3 hours Max Marks: 80
Answer any FIVE Questions
All Questions carry equal marks

1. Implement the following gates with p-MOS transistors only and explain its working
(a) 3 Input NAND gate.
(b) Inverter. [8+8]
2. Name different IC fabrication technologies with suitable examples. [16]
3. Explain details about level-1 modeling of MOS transistor. [16]
4. Compute the high-to-low delay of a two-input static complementary NOR gate with
minimum-sized transistor driving these loads.
(a) An inverter with minimum-sized pull up and pull down.
(b) An inverter whose pull up and pull down are both of size W = 10? L = 10?.
[8+8]
5. How cross-talk appears in ICs and explain how this cross-talk can be minimized in
ICs. [16]
6. Draw the Architecture of PLA and explain how different logic functions can be
implemented using PLA. [16]
7. Explain about pad design procedure to design input and output pads. [16]
8. Clearly explain about the generic integrated circuit design flow. [16]

1 of 1





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