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Posted By: sunil Member Level: Diamond Posted Date: 23 Jun 2008
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2008 III B.Tech II Semester Regular Examinations, Apr/May 2008 VLSI DESIGN Question paper
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Code No: R05320402
Set No. 3
III B.Tech II Semester Regular Examinations, Apr/May 2008
VLSI DESIGN
( Common to Electronics & Communication Engineering, Bio-Medical
Engineering and Electronics & Telematics)
Time: 3 hours
Answer any FIVE Questions
All Questions carry equal marks
? ? ? ? ?
Max Marks: 80
1. (a) What is Moore’s law? Explain its relevance with respect to evolution of IC
Technology.
(b) What is the size of silicon wafer used for manufacturing state-of-the art VLSI
ICs?
(c) What is the minimum feature size of current commercial VLSI devices?[8+4+4]
2. Compare the relative merits of three di?erent forms of pull up for an inverter
circuits. What is the best choice for realization in
(a) nMOS technology
(b) CMOS technology.
[16]
3. Draw the stick diagram and a translated mask layout for nMOS inverter circuit.
[16]
4. Describe three sources of wiring capacitances. Explain the e?ect of wiring capaci-
tance on the performance of a VLSI circuit.
5. (a) Compare the di?erent types of CMOS subsystem Multipliers.
[16]
(b) Design a schematic for an 8-word × 2-bit NAND ROM that serves a lookup
table to implement a full adder.
6. (a) Explain the methods of programming of PAL CMOS device.
(b) Draw and explain the architecture of an FPGA .
[8+8]
[8+8]
7. (a) What are the di?erent data types available in VHDL and how they are indi-
cated?
(b) Write a VHDL program for a 4-bit Counter with Asynchronous reset. [8+8]
8. (a) Draw the basic structure of parallel scan and explain how it reduces the long
scan chains.
(b) Draw the state diagram of TAP Controller and explain how it provides the
control signals for test data and instruction register.
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