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Posted By: Vidya Member Level: Diamond Posted Date: 08 Jul 2008
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2006 Guru Gobind Singh Indraprastha University B.Tech ETEC – 310 Subject : VLSI Design February 2006 Question paper
First-Term Examination
Sixth Semester [B.Tech] - February 2006
Paper Code : ETEC – 310 Subject : VLSI Design
Time : 11/2 Hours
Maximum Marks : 30
Note : Attempt any 3 questions in all. Q1 is compulsory. Each question carries 10 marks.
Q1
( a ) With a neat flow diagram discuss the VLSI design methodology.
[ 2]
( b ) Describe in brief about regularity, modularity and locality.[ 2 ]
( c ) Advantages and disadvantages of standard-cells based design.[ 2 ]
( d ) Noise margin in MOSFET inverter. [2 ]
( e ) Draw a neat diagram (isometric/oblique view) of an N-channel enhancement type MOSFET.[ 2 ]
Q2
( a ) Discuss in brief about:
Photolithography
Metallization and Polysilicon
Device isolation techniques
CMOS n-well process.
[10]
Q3
( a ) Write in brief about:
Law of mass action
Equilibrium Fermi level
Surface inversion
Threshold voltage
Channel length modulation
[5]
( b )
Derive the following relationship of an N-channel MOSFET:
see figure
(Where the notations have their usual meaning.)
Q4
( a )Discuss in detail the CMOS inverter with a resistive load and critical factors that affect the layout design. [10]
Attachments:
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