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Posted Date: 31 Jul 2007 Posted By: Girish Patil Member Level: Platinum
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2005 Shivaji University B.E Computer Science Computer Organization Question paper
Y-510
SECOND YEAR OF COMPUTER SCIENCE AND ENGINEERING (PART-2) EXAMINATION, 2005
SHIVAJI UNIVERSITY, KOLHAPUR
COMPUTER ORGANIZATION
Day and Date: Monday, 30-05-2005 Total Marks: 100
Time: 10.00p.m. To 1.00p.m.
Instructions: 1) Q.1 from section-1 and Q.5 from section-2 are compulsory.
2) Solve any two questions from Q.2, Q.3, and Q.4
3) Solve any two questions from Q.6, Q.7, and Q.8
4) Figures to right indicates full marks
SECTION-1
Q. 1 a) Illustrate the principle of restoring division technique.[Marks 5]
b) Compare the RISC and CISC processors.[Marks 5]
c) Design a full adder using multiplexer circuit.[Marks 5]
d) Explain the M/M/1 model of queuing.[Marks 5]
Q. 2 a) Give the detail design and working of binary fixed point multiplier.Marks 10]
b) Draw a block schematic indicating the data processing part of a simple floating-point arithmetic unit.[Marks 5]
Q.3 a) Explain desirable features of an instruction .Also describe the meaning of the term “completeness”.[Marks 8]
b) Describe the advantages of PLA what is meant by folded PLA and decoded PLA?[Marks 7]
Q.4 a) explains the algorithm for floating point multiplication and also gives the structure for realization of the floating point multiplication.[Marks 10]
b) Write a program to execute the statement:
X=A*B+C*C
In one address, two address and three address processor.[Marks 5]
SECTION-2
Q.5 a) Explain the working of microprogramming sequencer with help of neat diagram.[Marks 8]
b) Explain the operation of paged segmentation arrangement.[Marks 7]
c) Define programmed I/O. Give its advantages and disadvantages with respect to design complexity, I/O bandwidth and interface hardware costs.[Marks 5]
Q.6 a) with a suitable diagram, explain non-preemptive allocation algorithm for main memory.[Marks 5]
b) A typical CPU allows most interrupt requests to be enabled and disabled under software control, in contrast, no CPU provides Facilities to disable DMA request signals. Explain why this is so.[Marks 5]
c) Discuss the design steps involved in design of hardwired control unit using delay element method. [Marks 5]
Q.7 Write a short note on: [Marks 15=5*3]
1) I/O processor
2) High speed memories
3) Paging
Q.8 a) Give the advantage and disadvantages of DMA operation.[Marks 5]
b) Explain the working of interleaved memory organization with the help of neat diagram. [Marks 6]
c) Explain how interrupts processing carried out in typical CPU.[Marks 4]
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