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Posted By: ram Member Level: Diamond Posted Date: 03 Sep 2008
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2006 Jawaharlal Nehru Technological University II B.Tech II Semester Regular Examinations, Apr/May 2006 SWITCHING THEORY AND LOGIC DESIGN Question paper
Code No: RR222201 Set No. 2
II B.Tech II Semester Regular Examinations, Apr/May 2006
SWITCHING THEORY AND LOGIC DESIGN
(Instrumentation & Control Engineering)
Time: 3 hours Max Marks: 80
Answer any FIVE Questions
All Questions carry equal marks
? ? ? ? ?
1. (a) Perform the subtraction with the following unsigned binary numbers by taking
the 2’s complement of the subtrahend.
i. 11010-10000
ii. 11010-1101
iii. 100-110000
iv. 1010100-1010100
(b) The binary numbers listed have a sign bit in the left most position and, if nega-
tive, are in 1’s complement form. Perform the arithmetic operations indicated
and verify the answers.
i. 101011+111000
ii. 001110+110010
iii. 111001-001010
iv. 101011-100110
[8+8]
2. (a) Find the minimal expression for the function
f(w,x,y,z)=P(0,2,5,9,15) +Pd (6,7,8,10,12,13) using Karnaughs-map.
(b) i. Determine the Canonical sum-of-products form for T(x, y, z) = xy + z +
xyz
ii. Minimize the function f(x, y, z,w) = x + xyz + wx + xy + wx + xyz.
[8+4+4]
3. (a) Derive Boolean expression for a 2 input Ex-NOR gate to realize with two input
NOR gates, without using complemented variables and draw the circuit.
4. (a) Design a combinational circuit that accepts a 3-bit number and generates an
output binary number equal to the square of the input number.
(b) Realize a 3-bit odd-parity generator circuit using only two-input ex-or gate
[8+8]
5. (a) Obtain the excitation table for the given flip-flops
i. J-K-flip-flop
ii. D-flip-flop
(b) Draw the schematic circuit of S-R-Flip-Flop with negative edge triggering
using NAND gates and explain its operation with proper truth-table. Convert
this flip-flop to J-K flip-flop and explain its operation
[6+10]
6. Design a 4-bit universal shift register and draw the circuit with the given mode of
operation table.
S1 S0 Operation
0 0 Parallel
0 1 Shift right
1 0 Shift left
1 1 Inhibit clock
[16]
7. For the machine shown in the table below obtain:
(a) The corresponding reduced machine table in standard form
(b) Find a minimum length that distinguishes state A from state B where PS:
present state, NS: next state, Z: output, X: input
8. (a) Draw the state diagram and the state table of the control unit conditions given
below. Draw the equivalent ASM chart leaving the state box empty.
i. from 00 state, if x = 1 , it goes to 01 state and if x = 0, it remains in the
same state 00.
ii. from 01 state, if y = 1, it goes to 11 state and if y = 0, it goes to 10 state.
ii. from 10 stae, if x = 1 and y = 0, it remains in the same state 10 and if x
= 1 and y = 1, it goes to 11 state, and if x = 0, it goes to 00 state.
iv. from 11 state, if x = 1, y = 0, it goes to 10 state and if x = 1, and y =
1, it remains in the same state, and if x = 0, it goes to 00 state.
(b) Design the control using PLA and register.for the above problem.
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