My Profile
Active Members
TodayLast 7 Days
more...
Awards & Gifts
Online Exams
Fresher Jobs
Our fresher job section is exclusively for fresh graduates! Find jobs for freshers in major Indian
cities including Bangalore, Chennai, Hyderabad, Pune or Kochi
Resources
Find educational articles, blogs, discussion threads and other resources.
Colleges
Find details about any college in India or search for courses.
|
Download Model question papers & previous years question papers
|
Posted By: k vishaal Member Level: Gold Posted Date: 05 Sep 2008
|
2008 Jawaharlal Nehru Technological University Code No R05311403 Set No. 2,III B.Tech I Semester Supplimentary Examinations, February 2008,SWITCHING THEORY AND LOGIC DESIGN Question paper
|
|
|
Code No: R05311403 Set No. 2
III B.Tech I Semester Supplimentary Examinations, February 2008
SWITCHING THEORY AND LOGIC DESIGN
(Mechatronics)
Time: 3 hours Max Marks: 80
Answer any FIVE Questions
All Questions carry equal marks
? ? ? ? ?
1. Convert the following to Decimal and then to Binary.
(a) 101116
(b) ABCD16
(c) 72348
(d) 77668
(e) 12810
(f) 72010. [3+3+3+3+2+2]
2. (a) Draw the NAND logic diagram that implements the complement of the fol-
lowing function. [8]
F(A,B,C,D) = (0,1,2,3,4,8,9,12)
(b) Obtain the complement of the following Boolean expressions.
i. AB + A(B + C) + B’(B + D)
ii. A + B + A’B’C [4]
(c) Obtain the dual of the following Boolean expressions.
i. A’B + A’BC’ + A’BCD + A’BC’D’E
ii. ABEF + ABE’F’ + A’B’EF [4]
3. Apply Branching method to simplify the following function
F (A, B, C, D) =QM(0, 1, 4, 5, 9, 11, 13, 15, 16, 17, 25, 27, 28, 29, 31)d(20, 21, 22, 30).
[16]
4. (a) Realize Full Adder Using two half adders and logic gates.
(b) Draw the block diagram of BCD adder using two 4-bit parallel binary adders
and logic gates. [4+12]
5. (a) Derive the PLA programming table for the combinational circuit that squares
a 3 bit number.
(b) For the given 3-input, 4-output truth table of a combinations circuit,tabulate
the PAL programming table for the circuit. [8+8]
1 of 2
Code No: R05311403 Set No. 2
Inputs Output
x y z A B C D
0 0 0 0 1 0 0
0 0 1 1 1 1 1
0 1 0 1 0 1 1
0 1 1 0 1 0 1
1 0 0 1 0 1 0
1 0 1 0 0 0 1
1 1 0 1 1 1 0
1 1 1 0 1 1 1
6. Explain in detail the following:
(a) Johnson counter
(b) Serial binary adders
(c) Pulse mode & level mod sequential ckts. [5+5+6]
7. A clocked sequential circuit is provided with a single input x and single output Z.
Whenever the input produce a string of pulses 1 1 1 or 0 0 0 and at the end of the
sequence it produce an output Z = 1 and overlapping is also allowed.
(a) Obtain State - Diagram.
(b) Also obtain state - Table.
(c) Find equivalence classes using partition method & design the circuit using D
- flip-flops. [4+4+8]
8. (a) Draw the ASM chart for the following state transistion, start from the initial
state T1, then if xy=00 go to T2, if xy=01 go to T3, if xy=10 go to T1, other
wise go to T3.
(b) Show the exit paths in an ASM block for all binary combinations of control
variables x, y and z, starting from an initial state. [8+8]
? ? ? ? ?
2 o
Return to question paper search
|
|
|
Submit Previous Years University Question Papers and make money from adsense revenue sharing program
Are you preparing for a university examination? Download model question papers
and practise before you write the exam.
|
Watch TV Channels
|