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Posted Date: 24 Oct 2008 Posted By: vindhya Member Level: Diamond
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2008 Jawaharlal Nehru Technological University Computer Science & Engineering III B.Tech Supplimentary Examinations, Aug/Sep 2008,FAULT TOLERANT SYSTEMS Question paper
Code No: RR321503 Set No. 4
III B.Tech Supplimentary Examinations, Aug/Sep 2008
FAULT TOLERANT SYSTEMS
(Computer Science & Systems Engineering)
Time: 3 hours Max Marks: 80
Answer any FIVE Questions
All Questions carry equal marks
? ? ? ? ?
1. (a) A computer system contains 10,000 components each with failure rate 0.5%
per 1000 hours. What is the period of 0.99 reliability of this system.
(b) What is meant by active repair time and passive repair time referred in main-
tainability of a system. Derive the expression for the MTTR. [6+3+3+4]
2. (a) A circuit realizes the function.
Z=X1 X4+X2 X3+X1X4
Using Boolean Difference method find the test vectors for SA0, SA1 faults on
all input lines of the circuit.
(b) What are the different properties of Boolean differences? Explain [5+5+6]
3. (a) Design a redundant circuit for f = ab + a'b'
(b) Explain the Dynamic redundancy Technique of a fault Tolerant system.[8+8]
4. With an example explain :
(a) software redundancy.
(b) time redundancy. [8+8]
5. Design a totally self-checking checker for maximal-length Berger codes also give the
procedure to generate test vectors of 8 bit long. [8+8]
6. (a) Explain the advantages of PLA and how it is used as totally self-checking
circuit.
(b) For the given 4 input, 4 output function design a totally self checking checker
circuit using PLAs. [6+10]
f1 (A,B,C,D) = P (0,2,3,7,8,10,12,13,15)
f2(A,B,C,D) = P(0,2,3,4,9,12,13,15)
f3(A,B,C,D) = P(0,1,2,4,8,9,10,14)
f4(A,B,C,D) = P(0,1,2,4,5,6,8,11,14).
7. (a) Explain the Reed-Muller expansion Technique used in Design for testable cir-
cuit.
(b) Obtain the Reed Muller circuit for the given function. Also give the test set
for the same.
f = AB + AC + BC [8+4+4]
8. (a) Draw the logic diagram of Built-in Logic Block Observer.
(b) Discuss BILBO based BIST architecture.
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