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Posted Date: 26 Jan 2009 Posted By: kishore Member Level: Gold
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2006 Jawaharlal Nehru Technological University III B.Tech II Semester Regular Examinations, Apr/May 2006 ADVANCED COMPUTER ARCHITECTURE Question paper
Code No: RR320501 Set No. 2
III B.Tech II Semester Regular Examinations, Apr/May 2006
ADVANCED COMPUTER ARCHITECTURE
( Common to Computer Science & Engineering, Information Technology
and Computer Science & Systems Engineering)
Time: 3 hours Max Marks: 80
Answer any FIVE Questions
All Questions carry equal marks
? ? ? ? ?
1. Explain different parallel processing mechanisms that are possible in uniprocessor
computers. [16]
2. (a) Derive the expressions for efficiency, throughput and speed up for k stage
pipeline for n tasks.
(b) What are key issues in the design of an efficient dynamic pipeline processor.
[8+8]
3. (a) How are the two functions of a Shuffle Exchange are implemented?
(b) Compare the various Multistage SIMD Network. [10+6]
4. (a) Compare the two types of Associative Processor organizations.
(b) Differentiate between Bit-slice and Word-slice operations in STARAN. [10+6]
5. (a) List the several factors that affect the characteristics and performance of a
bus.
(b) Explain the different Bus arbitration algorithms. [4+12]
6. (a) List the major characteristics, advantages and shortcomings of three types of
multiprocessor operating systems.
(b) List the four main sources of performance degradation of the dynamic coher-
ence check algorithm. [12+4]
7. (a) Differentiate between dependence driven and multi level event driven approach
of designing data flow systems.
(b) Explain the functional design of a processor element in the EDDY system.
[8+8]
8. (a) How memory mapping is done in Cyber-205? Explain
(b) List various functions of virtual memory in Cyber 205.
(c) Describe any two special vector instruction of Cyber 205.
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