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Posted By: Sheethal Member Level: Gold Posted Date: 07 Feb 2008
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2006 Birla Institute of Technology-Mesra MS Software Engineering Comprehensive examination(open Book) University Question paper
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Birla Institute of Technology and Science, Pilani
Distance Learning Programmes Division
MS Software Engineering in Collaboration with Wipro Technologies
Second Semester 2005 – 2006
Comprehensive examination
Regular
Course No. : SEWPZC261
Course Name : Digital Electronics& Microprocessors
Nature of Exam : Open Book Exam
Weightage : 60 %
Duration : 3 Hours
Date : May 14, 2006 (AN)
Note: Attempt all questions. Start each answer from a fresh page
1 a).Design a mod-6 synchronous counter using JK Flip-Flops.
( State diagram+state table+transition table+ k-map simplification+logic ckt=1+1+2+2)
b)Show that a Jhonson counter with n flip-flops produces a sequence of 2n states.Assume n = 4
( logic ckt + o/p states =2+2)
2. Fig .2 shows the 3:8 decoder with three input signals:
IO/M’ , RD’ , and WR’ from the 8085 Microprocessor. Specify and name the valid o/p signals. (Function table+ valid o/p signals = 3+2)
Fig 2
3.a) In fig.3 , can you recognize whether it is the memory- mapped or the peripheral-mapped I/O? (Identification + reasoning= 1+1)
b) What is the port address if all the don’t care address lines are assumed to be at logic 0? (3)
Fig.3
4.Specify the contents of the registers and the flag status as the following instructions are executed. Assume the system clock as 2MHz.
A B C D S Z CY
MVIA, 00H
MVIB, F8H
MOVC,A
MOVD,B
HLT
Estimate the memory and time requirement for the program. (3+1+1)
5. Specify the register contents and the flag status as the following instructions are executed. Assume the system clock as 2MHz.
A B S Z CY
XX XX X X X ( INITIAL CONDITION)
SUBA
MOVB,A
DCRB
INRB
SUI 01H
HLT
Estimate the memory and time requirement for the program. (3+1+1)
6.a) Calculate the delay in the following loop, assuming the system clock period is 0.3 micro second.
Label Mnemonics T- states
LXIB,00FFH 10
DELAY: DCX B 6
XTHL 16
XTHL 16
NOP 4
NOP 4
MOVA,C 4
ORA B 4
JNZ DELAY 10 / 7
(Td=To+Tl=2+4 )
b) Calculate the maximum delay created in the following program segment.
LXIH, N (16 BIT COUNT)
L1: DCX H
MOVA,L
ORA H
JNZ L1.
Assume the system clock as 2MHz.
( Td=To+Tl=2+2)
7.Explain the functions of the following routines. Sketch the stack before and after the execution of the program segments.
a) LXI SP, 209FH b) LXI SP, stack
MVIC,00H PUSH B
PUSH B PUSH D
POP PSW POP B
RET POP D
RET.
(5+5)
8.a) If control word register of 8255 is 83H. Show the control word format and port configuration (mode of operation)
(Format+port usage+mode=1+2+2 )
b) If control word register of 8253 (8254) is B0 H. Show how each bit defines mode of operation, select counter, RD/WR and binary/ BCD counter.
(Format+counter usage +mode=1+2+2 )
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