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Posted Date: 01 Nov 2009      Posted By: teja      Member Level: Gold

2006 Jawaharlal Nehru Technological University B.Tech language processors Question paper



Course:   University: Jawaharlal Nehru Technological University




Code No: NR320504 NR
III B.Tech II Semester Supplementary Examinations, Apr/May 2006
LANGUAGE PROCESSORS
( Common to Computer Science & Engineering and Information
Technology)
Time: 3 hours Max Marks: 80
Answer any FIVE Questions
All Questions carry equal marks
? ? ? ? ?
1. (a) Explain lexical analysis in detail. [8]
(b) What are the reasons for separating lexical analysis from syntax analysis. [8]
2. (a) The grammar S ! aSa|aa generates all even length strings of a’s except for the
empty string-show that the brute force method of top down parsing succeeds
of 2,4 and 8a’s but fails on 6a’s. Also find out what are the even strings that
are passed by the technique. [8]
(b) What is an LL(1) grammar. Can you convert every context free grammar into
LL(1). [8]
3. (a) What is the difference between a syntax directed definite and translator scheme.
[8]
(b) Explain the algorithm for top down translator. [8]
4. (a) List out some typical semantic errors . Explain how they can be rectified? [8]
(b) What is static checking ? Give some examples of static checks. [8]
5. (a) Write detailed notes on the symbol table mechanism using tree data structure.
[8]
(b) Explain with an example about the symbol table mechanism using hash table
data structures. [8]
6. (a) Explain with an example the abstract machine code form of Intermediate code.
[8]
(b) Give a detailed account on loop optimisation techniques. [8]
7. (a) Augment the code generation algorithm to incorporate the following features.
[8]
i. The parenthesis in an expression
ii. Non commutative operators like ‘-‘ and ‘/’ etc
(b) Show various steps in the code generation algorithm of the expression
( a + b) / ( c + d)
Assuming two machine registers to be available. [8]
8. (a) Explain the memory requirement for variant I and variant II of intermediate
code of an assembler design. [8]
1 of 2
Code No: NR320504 NR
(b) How Declarative state and Assembler directives are processed by an assembler.
[8]
? ? ? ? ?
2 of 2





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