My Profile
Active Members
TodayLast 7 Days
more...
Awards & Gifts
Online Exams
Fresher Jobs
Our fresher job section is exclusively for fresh graduates! Find jobs for freshers in major Indian
cities including Bangalore, Chennai, Hyderabad, Pune or Kochi
Resources
Find educational articles, blogs, discussion threads and other resources.
Colleges
Find details about any college in India or search for courses.
|
Download Model question papers & previous years question papers
|
Posted By: acme Member Level: Silver Posted Date: 15 Apr 2008
|
2007 Jawaharlal Nehru Technological University B.E Computer Science VLSI SYSTEMS DESIGN Question paper
|
|
|
Code No: RR410505
IV B.Tech I Semester Regular Examinations, November 2007
VLSI SYSTEMS DESIGN
( Common to Computer Science & Engineering, Computer Science &
Systems Engineering and Electronics & Computer Engineering)
Time: 3 hours Max Marks: 80
Answer any FIVE Questions
All Questions carry equal marks
? ? ? ? ?
Set No. 1
1. Implement the following gates with n-MOS transistors only and explain its working
(a) 2 -Input NAND gate.
(b) 3 -Input NOR gate. [8+8]
2. An p-MOS transistor is operating in the triode region with the following parameters
µnCox = 95 µ A/V 2 W/L ( ratio) = 90 Vgs = -4V, Vtn = -1.1V, Vds = -2V .
Find its drain current & drain -Source resistance. [16]
3. Design a stick diagram for CMOS logic shown below.
Y = (A + B + C + D)1 [16]
4. Design a layout for CMOS 2-input NAND gate. [16]
5. Explain the procedure to optimize power consumption of an isolated logic gate.[16]
6. Draw the basic structure of serial-Parallel multiplier and explain its working principle.
[16]
7. Explain how Architecture driven voltage scaling technique reduces the power consumption
of the design. [16]
8. Draw the ASM chart for the kitchen timer controller. [16]
? ? ? ? ?
Set No. 2
I
1. Implement the following logic functions using CMOS logic
(a) Y = {AB + (C + D)}1
(b) Y = {A(B + C) + D}1 [8+8]
2. Explain working principal of n-MOS transistor with sketches of its structure. [16]
3. Design a stick diagram for CMOS, EX-OR and Inverter gates. [16]
4. Design a layout for CMOS 3-input NAND gate. [16]
5. Explain with suitable example the details of single - Row layout design method.
[16]
6. Draw the basic structure of serial-Parallel multiplier and explain its working prin-
ciple. [16]
7. Discuss some of the floor planning tips, such that the design can be easy - to-
implement and easy - to - change. [16]
8. Explain about switch - level simulation and give rules for evaluating switch - level
simulation. [16]
? ? ? ? ?
Set No. 3
1. Implement the following gates with CMOS Logic and explain its working
(a) 2 - Input AND gate.
(b) 4 - Input NOR gate. [8+8]
2. An n-MOS transistor is operating in the triode region with the following parameters
µnCox = 90µ A/V 2 W/L ( ratio) = 100 Vgs = 4V, Vtn = 1V, Vds = 2V . Find its
drain current & drain -Source resistance. [16]
3. Explain with neat sketches CMOS fabrication using twin - tub process. [16]
4. Implement 3-input NOR gate and 2 input AND gates using static complementary
logic. [16]
5. Define faults of a Digital circuit and Explain about struck at 0 /1 faulty models
[16]
6. Discuss clearly about the following system Design principles.
(a) Pipelining
(b) Data-paths [8+8]
7. Explain how power - down modes reduces the power consumption of the design.
[16]
8. Clearly explain about event driven simulation with suitable example. [16]
? ? ? ? ?
Set No. 4
1. Implement the following gates with n-MOS transistors only and explain its working
(a) 2 -Input NAND gate.
(b) 3 -Input NOR gate. [8+8]
2. Define different voltage parameters of digital IC and Explain their significance.[16]
3. With respect to IC fabrication explain about Design-rules and scalable design rules
[16]
4. Design a layout for CMOS 2-input AND gate. [16]
5. (a) With respect to testability of a Digital design define controllability and observability .
(b) Explain the properties of testable digital circuit. [8+8]
6. Draw the circuit diagram of four transistor DRAM cell with storage nodes and
explain its working. [16]
7. Explain clearly the detailed routing phase of the floor planning of the chip with
few examples by considering all constraints. [16]
8. Clearly explain about event driven simulation with suitable example. [16]
? ? ? ? ?
Return to question paper search
|
|
|
Submit Previous Years University Question Papers and make money from adsense revenue sharing program
Are you preparing for a university examination? Download model question papers
and practise before you write the exam.
|
Watch TV Channels
|