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Posted By: rajesh Member Level: Gold Posted Date: 29 Apr 2008
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2007 Shivaji University B.E Computer Science MICROPROCESSOR-1 Question paper Question paper
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Y-509
SECOND YEAR OF COMPUTER SCIENCE AND ENGINEERING (PART-2) EXAMINATION, 2007
SHIVAJI UNIVERSITY, KOLHAPUR
MICROPROCESSOR-1
Day and Date: Friday, 27-05-2007 Total Marks: 100
Time: 10.00a.m. To 1.00p.m.
Instructions:
1) Solve any THREE questions from SECTION-1
2) Solve any THREE questions from SECTION-2
3) Figures to right indicates full marks
SECTION-1
Q.1
a) Explain any five-assembler directives used in 8086 assembly language programming.
b) Write an 8086 assembly language program for block transfer of length 20 numbers from 6000H to 7000H
Q.2
a) Draw and explain 8086 maximum mode configuration. [Marks 8]
b) What is TYPE 0 interrupting in 8086? Hoe 8086 responds when it is invoked? [Marks 8]
Q.3 explain the following instructions in detail
a) MOVSW
b) IDIV
c) CBW
d) IRET
b) Discuss interrupt structure of 80386. [Marks 8]
Q.4
a) With neat diagram explain 8086 maximum mode configurations. [Marks 8]
b) Explain the system bus timing diagram for read cycle in minimum mode configuration [Marks 8]
SECTION-2
Q. 5)
a) How 80386 operate in real mode? Explain memory-addressing interrupt processing in this mode [Marks 8]
b) What is descriptor table? Draw LDT [Marks 8]
Q. 6)
a) Draw an internal architecture of 80386 and explain the operation of Barrel shifter adder. [Marks 8]
b) Explain memory addressing and interrupt processing in 808386 PVAM modes. [Marks 8]
Q.7)
a) Explain memory addressing in real mode [Marks 8]
b) Explain segment descriptor for 808386 CPU. [Marks 8]
Q.8)
a) Explain the role of segment selector in memory addressing with necessary figure. [Marks 8]
b) What is paging? Explain the address translation mechanism in paging for 80386. [Marks 8]
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