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2011 Anna University Chennai B.E Electronics & Communication Engineering VLSI NOV/DEC 2011(6th sem ECE) Question paper



Course: B.E Electronics & Communication Engineering   University/board: Anna University Chennai





B.E./B.Tech. DEGREE EXAMINATION, NOVEMBER/DECEMBER 2011.
Sixth Semester
Electronics and Communication Engineering
EC 2354 — VLSI DESIGN
(Regulation 2008)
(Common to PTEC 2354 – VLSI Design for B.E. (Part-Time) Fifth Semester
Electronics and Communication Engineering, Regulation 2009)
Time : Three hours Maximum : 100 marks
Answer ALL questions.
PART A — (10 × 2 = 20 marks)
1. Determine whether an NMOS transistor with a threshold voltage of 0.7 V is operating in the saturation region if GS V = 2 V and =DS V 3V.
2. Write down the equation for describing the channel length modulation effect in NMOS transistors.
3. Write the expressions for the logical effort and parasitic delay of n input NOR gate.
4. Why does interconnect increase the circuit delay?
5. Draw a pseudo NMOS inverter.
6. What are the advantages of differential flip flops?
7. State the objective of functionality test.
8. What are the test fixtures required to test a chip?
9. Write the Verilog module for an half adder.
10. What are the delay specifications available in Verilog HDL for modeling a
logic gate?
PART B — (5 × 16 = 80 marks)
11. (a) (i) An NMOS transistor has the following parameters : gate oxide thickness = 10 nm, relative permittivity of gate oxide = 3.9, electron mobility = 520 2 cm /V-sec, threshold voltage = 0.7 V, permittivity of free space = 14 10 85 . 8 - × F/cm and (W/L) = 8. Calculate the drain current when ( GS V = 2 V and = DS V 1.2 V) and ( GS V = 2 V and = DS V 2 V) and also compute the gate oxide capacitance per unit area. Note that W and L refer to the width and length of the channel respectively. (3 + 3 +
(ii) Draw and explain the DC and transfer characteristics of a CMOS inverter with necessary conditions for the different regions of operation. (8)
Or
(b) (i) Explain the gate, source/drain formation and isolation steps of CMOS fabrication process with neat diagrams. (8)
(ii) Give a brief note on the different process techniques to enhance the performance of CMOS transistors. (8)

12. (a) (i) Explain the static and dynamic power dissipation in CMOS circuits with necessary diagrams and expressions. (10)
(ii) Discuss the principle of constant field scaling and also write its effect on device characteristics . (6)
Or
(b) (i) Explain the different reliability problems related to the design of reliable CMOS chips. (10)
(ii) Give a brief account on design margin. (6)




13. (a) (i) Describe the basic principle of operation of dynamic CMOS, domino and NP domino logic with neat diagrams (12)
(ii) Write the basic principle of low power logic design (4)
Or
(b) (i) Compare the sequencing in traditional domino and skew tolerant domino circuits with neat diagrams. (8)
(ii) Explain the problem of metastability with neat diagrams and expressions. (8)

14. (a) Explain the manufacturing test principles in detail. (16)
Or
(b) Describe the adhoc testing and scan based approaches to design for testability in detail. (16)

15. (a) (i) Draw the three input CMOS NOR and NAND gates and write the Verilog switch level modeling for both. (10)
(ii) Explain the continuous and implicit continuous assignment with two suitable examples for each. (6)
Or
(b) (i) Draw the logic diagram of 4 to 1 MUX using NAND gates and write the gate level modeling using Verilog HDL. (8)
(ii) Give a brief note on the looping statements available in Verilog HDL and write a verilog code for D Latch. (6 + 2)





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