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Posted Date: 19 Jul 2012 Posted By:: Mandeep Member Level: Gold Points: 5 (Rs. 5)
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2011 Jawaharlal Nehru Technological University, Anantapur Jawaharlal Nehru Technological University, Anantapur III B.Tech Electrical and Electronics engineering II Semester(R07) Regular & Supplementary Examinations, April/May 2011 "VLSI Design" Set no:4 Question paper
Here is the old question paper of "VLSI Design" Set no:4 in 2nd semester exams of B.Tech Electrical and Electronics engineering 3rd year R07 at Jawaharlal Nehru Technological University, Anantapur in the year 2011. Feel free to download and prepare for your exams
Code :R7320206
III B.Tech II Semester(R07) Regular & Supplementary Examinations, April/May 2011
VLSI DESIGN
(Electrical & Electronics Engineering)
Time: 3 hours Max Marks: 80
Answer any FIVE questions
All questions carry equal marks
1. What are the four major CMOS technologies? Explain any one with flow chart.
2. Draw the circuit of a CMOS inverter. Draw and explain its DC characteristics.
3. Design a stick diagram for two input PMOS NAND and NOR gates.
4. What are the main sources of delay through a single gate? Mention the two possible solutions
for that delay and explain them with a neat diagram.
5. Compare carry select, carry skip and carry look ahead adders with respect to speed, area and
computing cost.
6. (a) Explain about the designing of a chip with sea of gates(SOG).
(b) Write about FPGA.
7. (a) Discriminate between logic level simulation and Switch level simulation.
(b) Write about Behavioral Synthesis.
8. Discuss in detail about the Boundary Scan architecture and its principle of testing the ICs at
board level.
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