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Posted Date: 27 Jul 2012 Posted By:: ANURAG GHOSH Member Level: Bronze Points: 5 (Rs. 4)
2012 West Bengal University of Technology (WBUT) B.Tech Computer Science and Engineering West Bengal University Of Technology,B.Tech. latest question papers for Computer Science and Engineering Students Question paper
Are you looking for the latest question papers of WBUT Computer Science And Engineering? Here is the previous year question paper of Computer Architecture from WBUT. This is the original question paper from the Computer Science and Engineering fourth semester exam conducted by West Bengal University of Technology in year 2012. Feel free to download the question paper from here and use it to prepare for your upcoming exams.
Time alloted: 3 hours Full Marks: 70
*Candidates are requested to give their answers in their own words as far as practicable.
Group - A
[Multiple Choice Type Questions]
1. Choose the correct alternatives for the following: Marks:[ 10 * 1 = 10 ]
i) A pipeline stage
a) is sequential circuit
b) is combinational circuit
c) consists of both sequential and combinational circuits
d) none of these
ii) Utilization pattern of successive stages of a synchonous pipeline can be specified by
a) Truth table
b) Excitation table
c) Reservation table
d) Periodic table
iii) SPARC stands for
a) Scalable Processor Architecture
b) Superscalar Processor A RISC Computer
c) Scalable Processor A RISC Computer
d) Scalable Pipeline Architecture
iv) Which of the following is not RISC architecture characteristic?
a) Simplified and unified format of code of instructions
b) No specialised register
c) No storage/storage instruction
d) Small register file
v) The time to access shared memory is same in which of the following shared memory
vi) Which of the following architectures corresponds to non-Neumann architecture?
vii) In absence of TLB, to access a physical memory location in a paged-memory system how many memory accesses are required?
viii) A direct mapped cache memory with n blocks is nothing but which of the following set associative cache memory organisations?
a) 0-way set associative
b) 1-way set associative
c) 2-way set associative
d) n-way set associative
ix) Portability is definitely an issue for which of the following architectures?
a) VLIW Processor
b) Super Scalar Processor
c) Super pipelined
d) None of these
x) Which of the following is not the cause of possible data hazard?
[Short Answer Type Questions]
Answer any THREE of the following. Marks: [3 * 5 = 15]
2. "Instruction execution throughput increases in proportion with the number of pipeline stages". Is this true?Justify your statement.
3. What are multiprocessor,multi-computer and multi-core systems ? Compare CISC and RISC computer architectures.
4. Describe Flynns classification of computer architecture.
5. How is a block chosen for replacement in set-associative cache to resolve a cache-miss?
6. How does principle of locality help in memory hierarchy design?
[Long Answer Type Questions]
Answer any THREE of the following. Marks: [ 3 * 15 = 45]
7. a) What is the difference between Computer Organisation and Computer Architecture?
b) Why does the equation to calculate the CPU-time of a program often expressed in terms of average CPI of that processor?
c) A 30% enhancement in speed-up for a component of the processor has been proposed for a new architecture.If the enhancement is usable only for 50% for the time,what is fraction of the time must enhancement be used to achieve an overall average speedup of 10?
d) What are the different approaches taken by pipeline processor to handle branch instructions? Briefly illustrate any two approaches.
8. a) What are the major hurdles to achieve this ideal spped-up?
b) Discuss data-hazard briefly.
c) Discuss briefly two approaches to handle branch hazards.
d) Consider a 4-stage pipeline that consists of Instruction Fetch(IF), Instruction Decode(ID),Execute(Ex) and Write Back(WB) stages.The times taken by these stages are 50 ns,60ns,110ns and 80ns respectively.The pipeline registers are required after every pipeline stage,and each of these pipeline register consumes 10ns delay.What is the speedup of the pipeline under ideal conditions compare to the corresponding non-pipelined implementation?
9. a) What do you mean by multiple issue processor?
b) Briefly describe the VLIW processor architecture.
c) What are the differences between superscalar processor and V.L.I.W. processor?
d) Suppose your program consists of 2500 instructions.The proportion of different kinds of instructions in the program is as follow:
Data transfer instruction 50%,arithmetic instruction 30%, and branching related instructions 20%.The cycles consumed by these types of instructions are 2,5 and 10 respectively.What will be the execution time for a 4Ghz processor to execute your program?
10. a) Discuss briefly MIMD architecture.
b) What is the significance of interconnection network in multiprocessor architecture?
c) An 8 kB 4-way set associative write back cache is organised as multiple blocks,each of 32-byte size.Assume that the processor generates 36 bits addresses.Calculate the total size of memory required by cache controller to store the tags for cache?
d) What are the approaches to improve miss penalty?
e) A CPU generates 32-bit virtual addresses.The page size is 4kB.The processor has a TLB which can hold a total of 256 page table entries.The TLB is an 8-way set associative.Calculate the TLB tage size.
11. Write short notes on any THREE of the following :
a) Vector stride
b) Non von Neumann architecture characteristics
c) Cache coherence problem and its solution
d) Cluster Computer
e) Amdahls law and its significance.
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