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Posted Date: 06 Aug 2012 Posted By:: Vikram Narang Member Level: Gold Points: 5 (Rs. 4)
2009 Punjab Technical University B.Tech Information Technology B.Tech IT, 3rd semester exam, Computer Architecture, PTU, December 2009 Question paper
Are you looking for the old question papers of B Tech IT,Punjab Technical University? Here is the previous year question paper from Punjab Technical University. This is the original question paper from the B.Tech IT third semester exam conducted by Punjab Technical University in year 2009. Feel free to download the question paper from here and use it to prepare for your upcoming exams.
Time : 03 Hours
Maximum Marks : 60
Instruction to Candidates:
1) Section- A is Compulsory from Section- B.
2) Attempt any Four questions from Section- C.
3) Attempt any Two questions
Section- A (10x2=20)
Q1)a) Convert the following logic function into min term
ABCDE + ABCDE, + ABCDE + ABCDE
b) Define the terms real time computer & process control computer.
c) Give the layered view of a computer system.
d) What is the role of Shift Registers digital computers?
e) Perform the subtraction with the following unsigned binary number by taking the 2s compliment
of the subtrahend
1 0 1 0 1 0- 1 0 1 0 1 0 0
f) Explain the meaning of the memory - reference
g) What is the difference between micro program and micro code?
h) What do you mean by software interrupt?
i) How Cache Memory is useful in memory hierarchy?
j) What do you mean by Interrupt - initiated I/O concept?
Section- B (4 x 5 = 20)
Q2) Explain brief about MIMD machines
Q3) Give an overview of CISC Architecture.
Q4) A computer employs RAM chip of 256*8 and ROM chips of 1024*8. The computer system needs 2K
bytes of RAM, 4K bytes of ROM and four interface units each with four registers. A memory – mapped I/O configuration is used. The two highest bits of the address bus are assigned 00 for RAM, 01 for ROM, and 10 for interface registers. Give the address range in the hexadecimal for RAM, ROM and interface.
Q5) A DMA controller transfers - bit words to memory using cycle stealing. The words are assembled characters a rate of at from a device that transmits per 2400 characters second. CPU is fetching and executing. The instructions per at an average of 1 million instructions second. By how much will the rate down because the DMA transfer?
Q6) Discuss the hardware implementation of division for signed magnitude data.
Section – C (2x10=20)
Q7) Explain in detail the main features at least two performance benchmarks.
Q8) (a) Explain why poor load balancing leads to less-than-linear speed up?
(b) A given processor has 32 registers, uses16-bit immediate has I42 and instructions in its ISA. In a given program,207oof the instructions take one input register and have one output register,307ohave two input registers and one output register,2570 have one output and one input register and take an immediate input as well, and the remaining2570 have one immediate input register and one output register. For each of how many bits are required? Assume that the four types of instructions, the ISA requires that all instructions be a multiple of 8 bits in length.
Q9) (a) How does pipelining improve performance?
(b) What is the result of the following operations when executed on a 8-bit processor uses a 2s complement representation negative integers?
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