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2014 Acharya Nagarjuna University B.Tech 2nd Year - Semester 1 - Digital Electronics - Bapatla Engineering College - June 2014 Question paper



Course:   University/board: Acharya Nagarjuna University

Are you looking for the previous question papers of Digital Electronics - Bapatla Engineering College - B.Tech? This is the original question paper from the B.Tech second year first semester exam conducted by Bapatla Engineering College in June 2014. Feel free to make a copy and use it to prepare for your upcoming exams.



II/IV B.Tech Degree Examinations, June 2014

First Semester

Digital Electronics



Time : 3 hours

Maximum Marks : 60



Answer question No.1 Compulsory

Answer ONE question from each Unit


1. Briefly explain following [12 x 1 = 12M]
a) Define byte?
b) Find the 2's complement of the binary number 10010010?
c) Add (23)8 and (67)8.
d) Simplify the expression ((A+B)+C)' using Boolean algebraic techniques?
e) What is a priority encoder?
f) Draw the logic circuit of 2 to 4 decoder?
g) What is a sequential circuit?
h) Define setup time?
i) What is a synchronous counter?
j) Define state diagram?
k) What is fan-in?
l) Define figure of merit?

UNIT - I [1 x 12 = 12M]

2. a) Convert the following decimal numbers into equivalent binary numbers.
i) 53.625
ii)4097.188
iii)167
2. b) Perform the following operations using 1's complement method and compare this method with the direct method.
i) (1010)2 – (1111)2
ii) (1010)2 – (1000)2. (OR)
3. a) Draw a circuit containing NAND gates only to realize XOR function.
3. b) Write the truth table of the function y'z+wxy'+wxz'+w'x'z

UNIT - II [1 x 12 = 12M]

4. a) Simplify the expression Y=Σm(7, 9, 10, 11, 12, 13, 14, 15) using K-map method.
4. b) Simplify the expression Y=m1+m5+m10+m11+m12+m13+m15 using K-map method. (OR)
5. a) Draw the block schematic and truth table for half adder. Explain the design approach for half adder using universal gates. Draw the relevant logic diagrams and present the necessary expressions.
5. b) Draw and explain the operation of 2's complement adder subtractor.

UNIT - III [1 x 12 = 12M]

6. a) Deduce the design procedure for sequential logic circuits. Give the classification of sequential logic circuits.
6. b) Explain synchronous and ripple counters. Compare their merits and demerits? (OR)
7. a) Realize D-FF and T-FF using JK-FF. Draw the logic diagrams and present their truth tables.
7. b) Draw and explain the logic diagrams for a 4-bit binary ripple down counter using positive edge triggered flip-flops.

UNIT - IV [1 x 12 = 12M]

8. a) Draw and explain the circuit diagram of a 3-input I2L NOR gate.
8. b) Draw the basic CMOS inverter and explain its operation. (OR)
9. a) Compare the characteristics of different logic families?
9. b) Draw a TTL circuit with totem pole output and explain its working. Why should it not be used for wired AND connection?





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