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Posted Date: 06 Jun 2009 Posted By:: Rajat Saini Member Level: Silver Points: 5 (Rs. 1)
2008 Kurukshetra University B.Tech B.tech Fourth semester. Question paper
Microprocessor and Interfacing
Paper :ECE-216 E
Time--Three hours][Maximum marks--100
Note:-- Attempt Five questions in all selecting at least one question from each unit.
question 1:- explain various types of interrupts in detail in 8085 microprocessor and describe the interrupt process for them in detail and what are the major issues in implementing the interrupts? 8+7+5=20.
question 2:- a) explain following instructions in detail with the help of examples:--
(iii) CALL addr (Label)
(v)XRI data 5x2.
b) Describe sequence of events that occurs when 8085 MPU reads from memory with the kelp of timing diagram. 10.
question 3. (a) Explain the following addressing modes with examples:--
i. Base Index Addressing Mode.
ii. Register Index Addressing Mode.
iii. Intra-segment indirect mode.
iv. Implicit Addressing mode. 4X3=12
b)construct the machine codes and give the addressing mode for the following instructions:-
i) ADD C17D[BX][DI], DX; opcode for ADD=000000
ii.MOV AX,[BX]; opcode for MOV =100010. 4X2=8
question 4.(a) Explain the following instructions with examples:-
iv. RET 4X3=12
b)Write an assembly language program to find any power of any number. 8.
Question 5 a) explain the features of mode '1' and node '2' of 8255 in detail. 6+6=12
b) interface 16-bit 8255 ports with 8086. address of port 'a' is FOH. draw interface circuitry. 8
Question 6. a) interface digital to analog converter of R-2R ladder type with an 8086 CPU running at 5MHz and write and an assembly language program to generate a sawtooth waveform of period 1 ms with V equal to 5 volt. take port 'a' as an output port. 12.
b) explain operation of successive approximation type analog to digital converter with the help of circuitry. 8.
Question 7 a) Explain the architecture and register organization of DMA controller (8237) in detail with diagram. 15
b) Explain the following modes of DMA operation with 8237 in detail:--
i. demand transfer mode
ii. cascade mode. 5.
question 8 a) give the architecture and signal description of programmable interval timer chip 8253 using diagram . 12.
b) give pin configuration of 8259 i.e priority interrupt controller. 8.
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