2010 Anna University Chennai B.E Computer Science and Engineering Cs2202  digital principles and system design Question paper
B.E/B.Tech. DEGREE EXAMINATION, NOVEMBER 2010 Third Semester Computer Science and Engineering CS2202  DIGITAL PRINCIPLES AND SYSTEM DESIGN (Common to Information Technology) (Regulation 2008) Time: Three hours Maximum : 100 Marks Answer ALL questions PART A  (10 X 2 = 20 Marks) 1. Find the octal equivalent of hexadecimal number AB.CD. 2. State and prove the consensus theorem. 3. Compare the serial and parallel adder. 4. Define look ahead carry addition. 5. Define priority encoder. 6. Write a dataflow description of a 2to1 line Mux using a conditional operator. 7. Differentiate Moore and Mealy circuit models. 8. What are the applications of shift registers? 9. What is meant by critical race? 10. What are the types of hazards?
PART B(5 X 16 = 80 Marks)
11. (a) Simplify the following 5 variable Boolean expression using McCluskey method. F=Em(0,1,9,15,24,29,30) + d(8,11,31). (16 Marks) (Or) (b) Determine the minterm sum of product form of the switching function. F= E(0,1,4,5,6,11,14,15,16,17,20,22,30,32,33,36,37,48,49,52,53,59,63). (16 Marks)
12. (a) Relative a BCD to Excess3 code conversion circuit starting from its truth table. (16 Marks) (Or) (b) Design a full adder and subtractor using NAND and NOR gates respectively. (16 Marks)
13. (a) (i) Define multiplexer. (ii) Implement the following boolean function using 8:1 MUX. F(A,B,C,D) = ABD + ACD + BCD + ACD (16 Marks) (Or) (b) Implement the switching functions z1= abde + abcde + bc + de z2= ace z3= bc + de + cde + bd z4= ace + ce using a 5X8X4 programmable logic array. (16 Marks)
14. (a) Design a clocked sequential machine using T flip flops for the following state diagram. Use state reduction if possible. Also use straight binary state assignment. (16 Marks) (Or) (b) Using RS FFs design a parallel counter which counts in the sequence 000,111,101,110,001,010,000,.... (16 Marks)
15. (a) Design a T flip flop from logic gates. (16 Marks) (Or) (b) Find a static and dynamic hazard free realization for the following function using (i) NAND gates. (ii) NOR gates. f(a,b,c,d) = Em (1,5,7,14,15) (16 Marks)
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