2007 Anna University Chennai B.E Electrical and Electronics Engineering semester Question paper
ANNA UNIVERSITY MODEL QUESTION PAPER B.E / B.Tech. Degree Examinations IF 242 DIGITAL SYSTEM DESIGN PART – A (10 x 2 = 20 Marks) 1. List the first 16 numbers in base 12. Use the letters A and B to represent the last two digits. Convert the numbers (546)12 to base 8. 2. Using DeMorgan’s theorem, convert the following Boolean expression to an equivalent expression that has only OR and complement operations. Show that the function can be implemented with logic circuits that have only OR gates and inverters: F = (y+z’) (x+y) (y’+z) 3. A combinational switching network has 4 inputs (A, B, C, D) and one output F. F= 0 if 3 or 4 of the inputs are 0. • Write the maxterm expansion for F. • Using AND and OR gates, find a minimum threelevel network to realize F. 4. What do you mean by positive logic, negative logic and mixed logic? 5. Realize the operation of a full adder using a 3x8 decorder. 6. Implement the following function with a multiplexer: F(A, B, C, D) = S(0, 1, 3, 4, 8, 9, 15) Use B,C and D as select lines. 7. With the help of a block diagram, explain the operation of a JK MasterSlave Flip flop. 8. Draw the logic diagram of a D Flipflop using NAND gates and derive its characteristic table. 9. What are the guidelines to be followed while making state assignments? 10. What are hardware description languages? PART – B (5 x 16 = 80 Marks) 11. i) In what way is the QuineMcCluskey method advantages over the Karnaugh method of simplifying a Boolean function? ii) Simplify the given Boolean function using QuineMcClukey, method: S (w,x,y,z) = S (1,4,6,7,8,9,10,11,15) 12a. i) Which are functionally complete sets of logic gates? Explain. ii) How are AND, OR and NOT operations realized with NAND gates? Using AND and OR gates, find a minimum network to realize f(a,b,c,d) = M1M2M5M9M10M14 using twolevel logic and threelevel logic. (OR) 12b. i) Convert the following network to all NAND gates, by adding bubbles and inverters where necessary. ii) Convert to all NOR gates. 13a. i) Discuss the usage of multiplexers in digital systems. ii) Explain with the help of a block diagram, a quadruple 2to1 line multiplexer. (OR) 13b. Realize the functions given below using a PLA. Give the PLA table and internal connection diagram for the PLA: F1 (a,b,c,d) = S (1,2,4,5,6,8,10,12,14) F2 (a,b,c,d) = S (2,4,6,8,10,11,12,14,15) 14a. Design a counter which counts the following sequence: 0,8,12,10,14,19,13,11,15,0,8,12, …. Use clocked JK flip flops and NAND gates. (OR) 14b. i) Specify the method that is used to construct a state table. ii) Describe with suitable examples, the two types of clockedsequential networks. 15a. i) What is an SM chart? In what way is it different from an ordinary flow chart? ii) Derive the SM chart for a binary multiplier control and explain the sequences indicated in the chart. (OR) 15b. i) Describe with suitable examples, the different conditions that can occur in a network. ii) With suitable examples, explain the hazards in combinational networks.  CS 233 — SYSTEM SOFTWARE PART A — (10 × 2 = 20 marks) 1. Define System Software. 2. Illustrate how input and output operations are performed in SIC. 3. Compare assembler and compiler. 4. List the types of assemblers. 5. What is a loader? 6. Give an example of data shared between PES. 7. Define macro. 8. What is conditional macro expansion? 9. List the various phases of a compiler. 10. What is debugging? PART B — (5 × 16 = 80 marks) 11. Write short notes on System Software tools with examples. 12. (a) Explain the various instruction formats provide atleast 3 examples for each. Or (b) Explain addressing modes in detail. 13. (a) Explain machine dependent assembler features. Or (b) Explain Assembler design options in detail. 14. (a) Explain Dynamic linking in detail. Or (b) Write short notes on machine independent loader features. 15. (a) Explain different types of linkers. Or (b) Explain the implementation of text editors in detail. CS 234 — DATABASE MANAGEMENT SYSTEM PART A — (10 × 2 = 20 marks) 1. Distinguish between physical and logical data independence. 2. What is a data dictionary? What are the informations stored in the data dictionary? 3. What is a view and how is it created? Explain with an example. 4. In what way is an Embedded SQL different from SQL? Discuss. 5. Which condition is called referential integrity? Explain its basic concepts. 6. Explain with a simple example, the lossless–join decomposition. 7. How to choose the best evaluation plan for a query? Explain. 8. What is a timestamp–ordering scheme? Specify two simple methods for implementing this scheme. 9. Give a comparison of object–oriented and object–relational databases. 10. Which are the two models used for discovering rules from database? Give the general form of rules to express knowledge. PART B — (5 × 16 = 80 marks) 11. (i) What are data models and how are they grouped? (ii) Explain in detail any two data models with sample databases. 12. (a) (i) Discuss the fundamental operations in the relational algebra. (ii) For each operation give an example. Or (b) (i) SQL language has several parts. What are they? (ii) How many clauses are there in the basic structure of an SQL? Explain. ( 13. (a) (i) Discuss the various pitfalls in a relational database design using a sample database. (ii) Explain at least two of the desirable properties of decomposition. Or (b) (i) What are the merits and demerits of a B+ tree index structure? (ii) Describe the structure of a B+ tree. (iii) How update operations are performed on B+ trees? 14. (a) With the help of a neat diagram, explain the basic steps involved in processing a query. Or (b) (i) What are the different types of storage media? (ii) Explain with a diagram, the block storage operations. 15. (a) (i) Draw a neat sketch to indicate the architecture of a distributed system. (ii) Explain the basic failure types in a distributed environment. (iii) Diagramatically represent the network topology used in a distributed system and explain the advantages and disadvantages of each configuration. ( Or (b) (i) Explain the architecture of a data warehouse with a neat diagram. (ii) What are the various issues to be considered while building a warehouse? Explain. EE 255 — ELECTRICAL ENGINEERING AND CONTROL SYSTEMS PART A — (10 × 2 = 20 marks) 1. State superposition theorem. 2. Give the algorithm for solving Loop Current Analysis. 3. Draw the equivalent circuit of a single phase transformer and name the components. 4. Draw Torque Versus armature current characteristics of D.C. shunt and series motors. 5. Explain briefly why single phase induction motor is not self starting. 6. Draw the circuit diagram of three phase rectifier using SCRs. 7. Show that the transfer function of canonical form of general block diagram with negative feed back is given by G(s) (1 +G(s) ·H (s)) 8. State Mason’s rule. 9. What is the need for state variable approach? 10. Give steady state error for step and velocity input. PART B — (5 × 16 = 80 marks) 11. A 10 kVA, 200/400 V, 50 Hz, single phase transformer gave the following test results. Open circuit test (hV winding open) 200 V, 1.3 A, 120 W. Short circuit test (lv winding short circuited) 22 V, 30 A, 200 W. 12. Calculate (i) magnetising current and the current corresponding to core loss at normal voltage and frequency (ii) parameters of equivalent circuit as referred to low voltage winding. (a) For the circuit shown in Fig. 12 (a), find the currents through R3 and R4 . Ea = 100 V; Eb = 40 V; R1 = R2 = R5 = 10 ohms = = R3 R4 20 ohms. Fig. 12 (a) Or (b) Two similar coils are magnetically coupled and their coefficient of coupling is 0.3. When the two are cumulatively connected in series, the total inductance is 100 mH. Calculate (i) self inductance of each coil (ii) total inductance when the coils are connected in series opposing connection (iii) the energy in the magnetic field with a current of 3 A and the two coils connected in both series aiding and series opposing connections. 13. (a) (i) Derive the torque equation of a d.c. motor. (ii) A 220 V shunt motor with an armature resistance of 0.5 ohm is excited to give constant field. At full load, the speed is 500 RPM and armature current is 30 A. If a resistance of 1 ohm is connected in series with the armature find the speed at full load torque. Or (b) Explain double field revolving theory applied to single phase induction motor and develop the equivalent circuit. 14. (a) (i) Explain the principle of operation of a shaded pole motor. (ii) Draw and explain the working of Mc–Murray inverter. Or (b) (i) Briefly explain open loop, closed loop and automatic control system. (ii) Using Mason’s rule, determine the transfer function of the signal flow graph shown in Fig. 14 (b). Fig. 14 (b) 15. (a) Obtain the state model of the electromechanical system shown in Fig. 15 (a). Fig. 15 (a) Or (b) (i) Explain time response specifications. (ii) A unity feed back system has the forward open loop transfer function 1 ( ) 10 + = s G s . Find the steady state error and the generalised error coefficients for r(t ) = t . MA 231 Mathematics III Part – A ( 10 × 2 = 20 Marks) 1. Form a partial differential equation by eliminating the arbitrary function f from ( z =( x + y)f (x2  y2 ). 2. Find the complete integral of q = 2px. 3. Find the half range sine series for f(x) = 2 in 0 < x < 4. 4. If the cosine series for f(x) = x sin x for 0 < x < p is given by ( ) S8 =   =   n 2 2 n cosnx, n 1 cos x 2 1 2 x sin x 1 1 show that .......... . 5.7 1 3.5 1 1.3 1 2 1 2 p = ?? ? ?? + ?  +  5. Classify the partial differential equation (1 x )z 2xyz (1 y )z xz 3x yzy 2z 0 2 yy x 2 xx xy  2  +  + +  = . 6. The steady state temperature distribution is considered in a square plate with sides x = 0, y = 0, x = a and y = a. The edge y = 0 is kept at a constant temperature T and the other three edges are insulated. The same state is continued subsequently. Express the problem mathematically. 7. Find the Laplace transform of . t et  e3t 8. Verify the initial value theorem for f(t) = 5 + 4 cos 2t. 9. If Fourier transform of f(x) is F(s), prove that the Fourier transform of f(x) cos ax is [F(s a) F(s a)] 2 1  + + . 10. Find the Fourier cosine integral representation of ( ) ? ? ? > < < = 0, x 1 1, 0 x 1 f x . Part – B ( 5 × 16 = 80 Marks) Question No. 11 has no choice; Questions 12 to 15 have one choice (either – or type) each. 11. (i) Expand in Fourier series of periodicity 2p of ( ) ? ? ? p  p < < p < < p = 2 x if x 2 x if 0 x f x . (ii) Find the halfrange cosine series for the function f(x) = x, 0 < x < p and hence deduce the sum of the series ( ) S8 n=0 + 4 . 2n 1 1 12. (a) (i) Find the complete solution and singular solution of z = px + qy + p2– q2. (ii) Find the general solution of x (z2  y2 )p + y (x2  z2 )q = z (y2  x2 ). (OR) (b) (i) Solve: (D2  4D'2 )z = cos2x coa 3y. (ii) Solve :[(D + D'  1)(D + 2D'  3)]z = 4 + 3x + 6y + e x + y . 13. (a) A taut string of length L is fastened at both ends. The midpoint of the string is taken to a height of b and then released from rest in this position. Find the displacement of the string at any time t. (OR) (b) A rod 30 cm long, has its ends A and B at 20ºC and 80ºC respectively, until steady state conditions prevail. The temperature at the end B is then suddenly reduced to 60º C and at the end A is raised to 40º C and maintained so. Find the resulting temperature u (x,t). 14. (a) (i) Find the Laplace transform of the function ( ) ? ? ? p < < p < < p = 0, t 2 sin t, 0 t f t and extending periodically with period 2p. (ii)Apply the Convolution theorem to find ( )( ) . s 9 s 125 L s 2 2 1 ? ?? ? ? ?? ? + +  (OR) (b) (i) Solve by using Laplace transform technique, y'' + 3y' + 2y = 2(t2 + t + 1), given that y(0) = 2 and y'(0) = 0. (ii) Find the inverse Laplace transform of ( ) ( ) . s 2s 7 4 s 1 2 + + 2  15. (a) (i) Find the Fourier transform of ( ) ? ? ? >  = = 0 for  x  1 1 x for x 1 f x . Hence evaluate the following integral: (ii) ? 8 ?? ? ?? ? 0 2 dx. x sin x (iii) ? 8 ?? ? ?? ? 0 4 dx. x sin x (OR) (b) (i) Find the Fourier sine and cosine transform of e2x . Hence find the value of the following integrals: (ii) ( ) ? 8 0 + x2 4 2 dx . (iii) ( ) ? 8 0 + 2 2 2 . x 4 x dx CS 232 — DIGITAL SYSTEMS PART A — (10 × 2 = 20 marks) 1. Find the hexadecimal equivalent of the octal number 153.4. 2. Show that the excess – 3 code is self–complementing. 3. State and prove Demorgan’s theorem. 4. Show that a positive logic NAND gate is the same as a negative logic NOR gate. 5. Distinguish between a decoder and a demultiplexer. 6. Derive the characteristic equation of a JK flip–flop. 7. State the relative merits of series and parallel counters. 8. What are Mealy and Moore machines? 9. A shift register comprises of JK flip–flops. How will you complement the contents of the register? 10. What is a dynamic hazard? PART B — (5 × 16 = 80 marks) 11. (i) Explain how you will construct an (n + 1) bit Gray code from an n bit Gray code. (ii) Determine the MSP form of the switching function F = S (0, 1, 4, 5, 6, 11, 14, 15, 16, 17, 20–22, 30,32, 33, 36, 37, 48, 49 52, 53, 59, 63) 12. (a) Implement the switching function whose octal designation is 274 using NOR gates only. Or (b) Design a switching circuit that converts a 4 bit binary code into a 4 bit Gray code using ROM array. 13. (a) Implement a binary serial adder using an SRFF programmable logic array. Or (b) Using D flip–flops, design a synchronous counter which counts in the sequence. 000, 001, 010, 011, 100, 101, 110, 111, 000. 14. (a) (i) Convert the following mealy machine into a Moore machine : Ns, Z x1 x2 PS 00 01 11 10 A A, 0 A, 1 B, 0 A, 1 B A, 1 B, 0 B, 1 B, 0 (ii) Minimise the following state table : Ns, Z x PS 0 1 A A, 0 D, 1 B C, 1 D, 0 C B, 0 E, 1 D D, 1 A, 1 E E, 0 G, 1 F G, 0 E, 0 G D, 1 A, 1 H D, 1 C, 1 Use Paull and Unger’s implication chart. Or (b) Using JK flip–flops, design a synchronous sequential circuit having one input and one output. The output of the circuit is a 1 whenever three consecutive 1’s are observed. Otherwise the output is zero. 15. (a) Implement the switching function tion F = S (0, 1, 3, 4, 8–12) by a static hazard free two level OR–AND gate network. Or (b) Show that no static 0 (static 1) hazard can happen in a two level AND–OR (OR–AND) realisation of a switching function F.
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