UNIT I:
INTRODUCTION: History. Why use VHDL ? Hardware design construction, design levels,
HDLs Hardware simulation and synthesis. Using VHDL for design synthesis, terminology.
PROGRAMMABLE LOGIC DEVICES :Why use programmable logic ? What is a
programmable logic device ? Block diagram, macrocell structures and characteristics of PLDs
and CPLDs. Architecture and features of FPGAs. Future direction of programmable logic.
UNIT II:
BEHAVIORAL MODELING:Entity declaration, architecture body, process statement, variable
assignment, signal assignment. Wait, If, Case, Null, Loop, Exit, Next and Assertion statements.
Inertial and transport delays, Simulation deltas, Signal drivers.
DATA FLOW AND STRUCTURAL MODELLING:Concurrent signal assignment, sequential
signal assignment, Multiple drivers, conditional signal assignment, selected signal
assignment, block statements, concurrent assertion statement, component declaration,
component instantiation.
UNIT III:
GENERICS AND CONFIGURATIONS :Generiecs, Why configurations ?, default
configurations, component configurations. Generiecs in configuration. Generic value
specification in architecture, block configurations, architecture configurations.
SUBPROGRAMS AND PACKAGES :Subprograms – functions, procedures, declarations.
Package declarations, package body, use clause, predefinal package standard. Design libraries,
design file.
UNIT IV:
ADVANCED TOPICS :Generate Statements, Aliases, Qualified expressions, Type conversions,
Guarded signals, User defined attributes, Predefined attributes., VHDL synthesis.
Reference http://www.IndiaStudyChannel.com/r/karangoel.aspx
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