VHDL Program of 4 bit Parallel Adder

In this article we will write a program of 4 bit parallel adder in VHDL. 4 bit parallel adder is used to add two 4 bit data. So four full adders are required to construct the 4 bit parallel adder. Now full adder is used to add 3 bit together and gives output as sum and carry.

First we define the expression of sum and carry that we will use in the program.The expression is given below:

sum= a xor b xor c
carry= a and b or b and c or c and a

Note: a,b,c are three input bits which are to added and sum and carry are the outputs of the adder.

In order to write the program first we have to declare the entity and determine total inputs and outputs we require. As we have to add two 4 bit data we declare two inputs as a and b of 4 bits. The output of program will have sum and carry so we also define sum and carry outputs as s and c of 4 bits. We will require one more input of 1 bit which will contain the carry coming from previous data so we define it as cin. Now our entity is defined let us define the architecture of the program. First we define a variable of std_logic type which will contain the value of cin. Now we use for loop in order to take one bit at a time and get the required output one by one in each bit. So the loop will run 4 times for 4 bit data. The coding of program is given below:

library IEEE;

-- Uncomment the following lines to use the declarations that are
-- provided for instantiating Xilinx primitive components.
--library UNISIM;
--use UNISIM.VComponents.all;

entity pa1 is
Port ( a : in std_logic_vector(3 downto 0);
b : in std_logic_vector(3 downto 0);
s : out std_logic_vector(3 downto 0);
c : out std_logic;
cin : in std_logic);
end pa1;

architecture pa11 of pa1 is

variable u:std_logic;
for i in 0 to 3 loop
s(i)<=a(i) xor b(i) xor u;
u:=(a(i) and b(i))or(b(i) and u) or(u and a(i));
end loop;
end process;

end pa11;

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