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INTEL CORE 2 QUAD ARCHITECTURE
Posted Date: 08 May 2008 Resource Type: Articles/Knowledge Sharing Category: Computer & Technology
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Posted By: pournami Member Level: Gold
Rating:  Points: 2
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INTEL CORE 2 QUAD ARCHITECTURE
Kentsfield, the code name for the quad-core chip, is literally two dies built into a single multi-chip module. Kentsfield uses two dies in a single package and each die is a dual core unit, for a total of four cores on the processor. The reasoning behind using a two-die configuration is really one of engineering and money; its much easier (and thus cheaper) to glue two dies on a single processor package and thus the time to market is lower as well.
Each core still has 4MB of shared L2 cache for a total of 8MB L2 on the processor; the L2 cache is only shared locally on each core so each pair of cores (one on each die) has access to the other's memory via very quick access. However, if one core wants to access data or "talk" to another core on the other die, the communication occurs over the front-side bus (FSB) as there isn't any internal communication logic between the two dies. The FSB between the processor and the chip still runs at 1066 MHz by default as well.
On Intel quad-core CPUs the Front Side Bus is used for accessing the RAM memory, other devices present on the PC and for the communication between each pair of cores. The communication between each pair of cores can be done up to 8 GB/s.
The L2 memory cache is shared, meaning that both cores use the same L2 memory cache, dynamically configuring how much cache each core will take. One core may be using 3.5 MB while the other 512 KB (0.5 MB), contrasted to the fixed 50%-50% division used on previous dual-core CPUs.
FEATURES AND BENEFITS OF INTEL PROCESSOR
1. Intel ® Wide Dynamic Execution
Improves execution speed and energy efficiency, delivering more instructions per clock cycle. Each of the four cores can complete up to four full instructions simultaneously.
Intel Wide Dynamic Execution also includes a new and innovative capability called Macro-Fusion. Macro-Fusion combines certain common x86 instructions into a single instruction that is executed as a single entity.
2. Intel ® Smart Memory Access
Intel Smart Memory Access improves system performance by optimizing the use of the available data bandwidth from the memory subsystem and hiding the latency of memory accesses. The goal is to ensure that data can be used as quickly as possible and is located as close as possible to where it is needed to minimize latency and thus improve efficiency and speed.
Intel Smart Memory Access also includes an instruction pointer-based prefetcher that “prefetches” memory contents before they are requested so they can be placed in cache and readily accessed when needed. New pre-fetch algorithms move data from system memory into fast L2 cache in advance of execution. These functions keep the pipeline full, improving instruction throughput and performance.
Intel Smart Memory Access includes an important new capability called "memory disambiguation," which increases the efficiency of out-of-order processing by providing the execution cores with the built-in intelligence to speculatively load data for instructions that are about to execute before all previous store instructions are executed.
3. Intel ® Advanced Smart Cache
Intel Advanced Smart Cache is a multi-core optimized cache that improves performance and efficiency by increasing the probability that each execution core of a dual-core processor can access data from a higher-performance, more-efficient cache subsystem. To accomplish this, Intel Core microarchitecture shares the Level 2 (L2) cache between the cores. This better optimizes cache resources by storing data in one place that each core can access.
By sharing L2 cache between each core, Intel Advanced Smart Cache allows each core to dynamically use up to 100 percent of available L2 cache. Threads can then dynamically use the required cache capacity. As an extreme example, if one of the cores is inactive, the other core will have access to the full cache. Intel Advanced Smart Cache enables very efficient sharing of data between threads running in different cores. It also enables obtaining data from cache at higher throughput rates for better performance. Intel Advanced Smart Cache provides a peak transfer rate of 96 GB/sec (at 3 GHz frequency).
4. Intel ® Advanced Digital Media Boost
Another new feature found on Core microarchitecture is a true 128-bit internal datapath. On previous CPUs, the internal datapath was of 64 bits only. This was a problem for SSE instructions, since SSE registers, called XMM, are 128-bit long. So, when executing an instruction that manipulated a 128-bit data, this operation had to be broke down into two 64-bit operations.
The new 128-bit datapath makes Core microarchitecture faster to process SSE instructions that manipulate 128-bit data. Intel is calling this new feature “Advanced Digital Media Boost”.
Advanced Digital Media Boost accelerates the execution of Streaming SIMD Extension (SSE) instructions to significantly improve the performance on a broad range of applications, including video, audio, image and photo processing, multimedia, encryption, financial, engineering and scientific applications. The 128 bit SSE instructions are now issued at a throughput rate of one per clock cycle effectively doubling their speed of execution on a per clock basis over previous generation processors. (Intel® Advanced Digital Media Boost executes 128-bit SSE instructions in a single clock cycle.)
5. Intel Virtualization Technology (Intel VT)
Allows one hardware platform to function as multiple “virtual” platforms. Intel ® VT improves manageability, limiting downtime and maintaining worker productivity by isolating computing activities into separate partitions.
6. Intel ® 64 Architecture
Allows the processor to access larger amounts of memory. Intel 64 architecture improves performance by allowing systems to address more than 4 gigabytes (GB) of both virtual and physical memory.
Intel 64 provides support for:
· 64-bit flat virtual address space
· 64-bit pointers
· 64-bit wide general purpose registers
· 64-bit integer support
· Up to one terabyte (TB) of platform address space
7. Execute Disable Bit
Provides extended virus defense when deployed with a supported operating system. Memory can be marked as executable or non-executable, allowing the processor to raise an error to the operating system if malicious code attempts to run in non-executable memory. This can prevent the code from infecting the system. Replacing older computers with Execute Disable Bit-enabled systems can halt worm attacks, reducing the need for virus-related repairs.
8. Digital Thermal Sensor (DTS)
Provides for more efficient processor and platform thermal control improving system acoustics. The DTS continuously measures the temperature at each processing core. The ability to continuously measure and detect variations in processor temperature enables system fans to spin only as fast as needed to cool the system. The combination of these technologies can result in significantly lower noise emissions from the PC.
9. Intel® Intelligent Power Capability
Intel Intelligent Power Capability is designed to reduce power consumption and design requirements. This feature manages the runtime power consumption of all the processor's execution cores. It includes an advanced power-gating capability that allows for an ultra fine-grained logic control that turns on individual processor logic subsystems only if and when they are needed. The result is excellent energy optimization enabling Intel Core microarchitecture to deliver more energy-efficient performance for desktop PCs, mobile PCs and mainstream servers.
10. Intel Designed Thermal Solution for Boxed processors
Includes a 4-pin connector for fan speed control to help minimize the acoustic noise levels generated from running the fan at higher speeds for thermal performance. Fan speed control technology is based on actual CPU temperature and power usage.
 Attachments
Figure 2: Quad Core Intel Processor Architecture (16161-81356-INTEL CORE 2 QUAD ARCHITECTURE.doc)
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Responses
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| Author: Prasad 18 May 2008 | Member Level: Gold Points : 2 | Good Information
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