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Faculty Development Programme on VLSI Design
24 May 2008 – 30 May 2008
Coordinators
Dr. J.Raja Paul Perinbam
Mr.R.Seshasayanan
About the Course:
The objective of the Faculty Development Programme is to give a better exposure to the faculty members on the subject “EC1401 VLSI Design”. The course
covers detailed theory, tutorials and HDL simulation practices.
The outline of the course is as follows:
CMOS Technology: nwell – pwell –Twin tub – Interconnections Latch up - Layout
rules-CAD Tool- Design Hierarchy. MOS Transistor theory : Threshold Voltage – AC/DC Characteristics – Noise margin – Rise / Fall Time – Transmission
Gate. VERILOG HDL: Structural - Behavioral – RTL Module Examples of Latches –
Adders. CMOS Chip Design: Logic Gates - CMOS Muxes and Latches – ASIC – PAL –
Programmable Gate Array. CMOS Testing : Manufacturing – Chip level –System level test techniques.
Who Can Participate?
Teachers from affiliated and non-affiliated
engineering colleges.
Course Fee:
1. No course fee for the first 20 registrants from affiliated colleges of Anna University,Chennai.
2. Additional participants may be considered provided each additional participants pays Rs.500/- in the form of Demand Draft in favor of “The HOD, Dept. of ECE, Anna University Chennai” Payable at Chennai.
Venue:
Department of Electronics and
Communication Engineering
College of Engineering Guindy Campus
Anna University Chennai
Chennai 600025
Last Date for Registration: 18.05.2008
Acceptance will be intimated on or before
19.05.2008 through E-mail only.
For Further Details,
Contact:
Phone: 044-22203170
044-22203174-301
E-mail: jrpp@annauniv.edu
For more details, visit http://www.annauniv.edu
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