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504191 ELECTIVE III
FAULT TOLERANT SYSTEM DESIGN
Teaching Scheme Examination Scheme
Lectures: 3 Hrs./Week Theory: 100 Marks
Credit: 3
Modeling: Basic Concept, Functional modeling at the logic level, Functional models at the register
level, Structural models, Level of modeling. Type of simulation, unknown logic value, compiled
simulation, Event-driven simulation and Hazard Detection. Logical fault models, Fault detection and
redundancy, Fault equivalence and fault location, Fault Dominance, Single stuck-fault models,
multiple stuck fault model, stuck RTL variables, Fault variables. Testing for Single Stuck fault and
Bridging fault. General fault simulation techniques, Serial Fault simulation, Parallel fault simulation,
Deductive fault simulation, Concurrent fault simulation, Fault simulation for combinational circuits,
Fault sampling, Statistical fault analysis. General aspects of compression techniques, ones- count
compression, transition – count compression, Parity – check compression, Syndrome testing and
Signature Analysis Basic concepts , Multiple – Bit Errors , Checking circuits and self checking , self
– checking checkers , Parity – check function , totally self-checking m/n code checkers , totally selfchecking
equality checkers , Self-checking Berger code checkers and self checking combinational
circuits.Built In Self Test, Self testing circuits for systems, memory & processor testing, PLA
testing, Automatic test pattern generation and Boundary Scan Testing JTAG
References:
1. M.Abramovici, M.A. Breuer, A.D. Friedman, “Digital systems testing and testable design”,
Jaico Publishing House.
2. Diraj K. Pradhan, “Fault Tolerant Computer System Design”, Prentice Hall.
For more details, visit http://www.unipune.ernet.in/stud_info/Syllabi/Syllabus_2008.html
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