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Syllabus of University of Pune ME E & TC VLSI & Embedded Systems Semester I-ADVANCED DIGITAL SYSTEM
504191 ELECTIVE III
ADVANCED DIGITAL SYSTEM DESIGN
Teaching Scheme Examination Scheme
Lectures: 3 Hrs./Week Theory: 100 Marks
Digital System Design aspects for RISC and CISC CPU architectures. Control and Data path
units of Processor. Practical design aspects for high frequency digital design such as clock skew and
synchronous / asynchronous input signal handling. Hazard analysis, fault tree analysis. Estimation of
digital system reliability. System integrity. Design of digital system for network applications such as
ATM switch design, ATM packet generator, ATM packet decoder. Hardware testing and design for
testability: Testing combinational and sequential logic, scan testing, boundary scan and BIST.
VHDL models for memories and buses such as SRAM memory, 486 bus model and memory
interfacing with microprocessor bus. Floating point arithmetic operations such as multiplications
and others. Digital system design for asynchronous serial data transfer.
1. John F. Wakerly,”Digital Design principles and practices”,3rd edition, PHI publications.
2. Charles H. Roth, ”Digital system design using VHDL”, Thomson Publication.
3. Balabanian,”Digital logic design principles”,Wiley publication.
4. Stephen Brown, “Fundamentals of digital logic”, TMH publication.
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