504192 ELECTIVE IV (OPEN)
SYSTEM-ON-CHIP (SoC)
Teaching Scheme Examination Scheme
Lectures: 3 Hrs./Week Theory: 100 Marks
Credit: 3
IC Technology, Economics, CMOS Technology overview, Power consumption, Hierarchical design,
Design Abstraction, EDA tools. MOSFET model, parasitics, latch up, advanced transistor structures;
Wire parasitics; Design rules, Scalable design rules, process parameters; stick diagrams, Layout
design tools; Layout synthesis, layout analysis. CMOS gate delays, transmission time, speed power
product, low power gates; Delay by RC trees, cross talk, RLC delay, cell based layout, Logic &
interconnect design, delay modeling, wire sizing; Power optimization, Switch logic networks.
Pipelining, Data paths, Adders, ALUs, Multipliers, High density memories; Metastability,
Multiphase clocking; Power optimization, Design validation, Sequential testing; Architecture for low
power. Floor planning methods, global routing, switch box routing, clock distribution; off chip
connections, packages, I/O architectures, pad design. Complete chip design including architecture,
logic and layout for Kitchen timer chip OR Microwave oven chip.
References
1. Wayne Wolf, “Modern VLSI Design”, Pearson Education.
2. Kamaran Eshraghian, “Principles of CMOS VLSI Design”, Pearson Education
3. Rabey, Chandrakasan, “Digital IC Design”, Preason Publication.
Reference http://www.unipune.ernet.in/stud_info/Syllabi/Syllabus_2008.html
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