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A Combined Hardware-Software Approach for Low-Power Embedded Applications
Posted Date: 05 Oct 2008 Resource Type: Articles/Knowledge Sharing Category: Computer & Technology
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Posted By: ketan Member Level: Gold
Rating:  Points: 2
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Low power consumption is arguably the most important feature of embedded processors, which significantly impacts the cost and physical size of the end device. Even though the processor may not be the most power-hungry component of a system, it is essential to manage processor power in order to reduce overall system power consumption. Better processor power efficiency can increase the available power budget for features such as color screens and backlights, which are growing in popularity on portable devices. Historically, low power consumption in embedded processors has been achieved through simple designs, limited use of speculation, and employing a number of low-power sleep modes that reduce idle-mode power consumption. Embedded processors are now performing more sophisticated tasks, which require ever-higher performance levels. As a result, new processor designs are more dependent on sophisticated architectural techniques (such as prediction and speculation) to achieve high performance. Unfortunately, such techniques can also significantly increase the processor’s power consumption. Process technology trends are also complicating the power story. Until recently, CMOS transistors consumed negligible amounts of power under static conditions. However, as process geometries shrink to provide increasing speed and density, their static (leakage) power consumption has also increased. Current estimates suggest that static power accounts for about 15%-20% of the total power on chips implemented in 0.13µm high-speed processes. Moreover, as process technology moves below 0.1µm, static power consumption is set to increase exponentially, and will soon dominate the total power consumed by the processor.
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