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Intel 8086 Architecture
Posted Date: 09 Jan 2008 Resource Type: Articles/Knowledge Sharing Category: General
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Posted By: ashish Member Level: Diamond
Rating:  Points: 5
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Quick Reference List
adc Add with carry flag
add Add two numbers
and Bitwise logical AND
call Call procedure or function
cbw Convert byte to word (signed)
cli Clear interrupt flag (disable interrupts)
cwd Convert word to doubleword (signed)
cmp Compare two operands
dec Decrement by 1
div Unsigned divide
idiv Signed divide
imul Signed multiply
in Input (read) from port
inc Increment by 1
int Call to interrupt procedure
iret Interrupt return
j?? Jump if ?? condition met
jmp Unconditional jump
lea Load effective address offset
mov Move data
mul Unsigned multiply
neg Two's complement negate
nop No operation
not One's complement negate
or Bitwise logical OR
out Output (write) to port
pop Pop word from stack
popf Pop flags from stack
push Push word onto stack
pushf Push flags onto stack
ret Return from procedure or function
sal Bitwise arithmetic left shift (same as shl)
sar Bitwise arithmetic right shift (signed)
sbb Subtract with borrow
shl Bitwise left shift (same as sal)
shr Bitwise right shift (unsigned)
sti Set interrupt flag (enable interrupts)
sub Subtract two numbers
test Bitwise logical compare
xor Bitwise logical XOR
Detailed Instruction List
A complete listing of all x86 instructions along with usage and encoding information can be found in the NASM Manual (852 KB). However, when using this manual, be careful to only use instructions compatible with the 8086. The Am186/Am188 Instruction Set Manual (2,242 KB) contains a more detailed description of instruction behavior for instructions compatible with the 8086. However, these AMD processors also support the following x86 instructions which are not 8086 compatible: bound, enter, ins, leave, outs, popa, and pusha.
Important Usage Notes:
1. The first operand of an instruction is also the destination if there is a resulting value. Divide and multiply instructions are common exceptions to this rule.
2. There can be at most one memory operand per instruction.
3. There can be at most one immediate operand per instruction.
4. Operands generally must be of the same size (i.e., byte or word).
5. Using a label is the same as using an immediate or constant value.
6. When BP is used in a memory reference, SS is assumed as the segment. Otherwise DS is assumed.
7. While an instruction is executing, IP refers to the next instruction.
8. Many instructions are smaller if you use the appropriate registers (usually AX or AL).
9. In NASM, all labels are case sensitive but instruction and register names are not.
Terminology Used:
• memory - Refers to an 8 or 16-bit memory location determined by an effective address.
• register - AX, BX, CX, DX, SI, DI, BP, or SP as well as the 8-bit derivatives of AX, BX, CX, and DX (other registers or flags are not allowed).
• immediate - A numeric constant or label.
• REG1::REG2 - The concatenation of two registers (e.g., the 32-bit value DX::AX) A single colon is used for memory addresses.
• XF or XF=b - A flag's value after an instruction can be 0 or 1 and usually depends on the result of the instruction. A flag being set to '?' by an instruction indicates that the flag is undefined after the operation.
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