Digital Electronics & Logic Design 4

Posted Date: 30 Jan 2008 Resource Type: Articles/Knowledge Sharing Category: General

Posted By: piyush Member Level: Gold
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Points: 3

Subject: Digital Electronics & Logic Design

Q1. Explain the operation of SR latch using NAND gates and NOR gates.
Q2. Write the truth table for SR, JK, D and T flip
Q3. From the truth table derive excitation table for all the flip flops.
Q4. What is race around condition ? What are the different ways to remove this limitation?
Q5. Differentiate different types of counters.
Q6. Design modulo-18 synchronous and asynchronous counter.
Q7. Explain the working of 5-bit ring counter and twisted ring counter.
Q8. Explain the use of preset and clear terminal of flip-flops.
Q9. Draw the circuit for 5-bit register.
Q10. Draw the circuit for 5-bit shift register. How many pulses are needed for following conversions?
(i) Serial i/p to parallel o/p data conversion
(ii) Serial i/p to serial o/p data conversion
(iii) Parallel i/p to parallel o/p data conversion
(iv) Parallel i/p to serial o/p data conversion
Explain with the clock cycle, how data 11101 propagates through this shift register?
Q11. Design a 3-bit binary up-down counter using mode control(M) input.
Q12.Convert JK flip flop to YZ flip flop, where truth table for YZ flip flop is given below:
Y Z Q(n+1)
0 0 Q(n)
0 1 Q’(n)
1 0 0
1 1 1

Also write excitation table for YZ flip-flop.
Q13.What is the advantage of synchronous counters on asynchronous counters?
Q14. Design a random generator which generates sequence 1011001011----

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