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Interfacing devices and phripheral devices :-


Posted Date: 03-Feb-2008  Last Updated:   Category: Computer & Technology    
Author: Member Level: Silver    Points: 5



INTERFACING DEVICES:

3.1 Introduction:
Microprocessor-based system design involves interfacing the proces¬sor with one or more peripheral devices, Microprocessor can send or receive data from the I/O devices.
3.2 Types of Interfacing Devices.
The Interfacing devices are classified as:
1. General purpose peripherals,
2. Special purpose peripherals.
General purpose peripherals are devices that perform a specific task.
General purpose peripherals are:
1. An I/O port
2. Programmable Peripheral Interface (PPI)
3. Programmable Interrupt Controller (PIC)
4. Programmable DMA Controller
5. Programmable Communications Interface
6. Programmable Interval Timer.
Special purpose peripherals are:

1. Programmable CRT Controller
2. Programmable Floppy Disk Controller
3. Programmable Hard Disk Controller
4. Programmable Keyboard and Display Interface.

3.4 Address decoding for I/O:

SEVEN-SEGMENT LED:


Fig : 3.0 7 – segment LED

Figure 3.0 shows the SEVEN – segment LED.A seven-segment LED consists of 7- light-emitting diode segments and one segment for the decimal point. For example, to display an 8, all segments must be’ON’.
The Seven-segment LEDs are divided in to two types,
1. Common anode
2. Common cathode
the LED’s Current limit is 20 mA. , D0 – D 6 lines are connected to the segments A, B,C,D,E,F and G respectively. If the decimal point is required, the segment (DP) is to be connected to data line D7. The following fig shows the decoding circuits of LED’s, which has the latch circuits and the current limiters.

figure 3.1 : Interfacing of 7 –segment LED

INTERFACING CIRCUIT AND ITS ANALYSIS

To design an output port with the address F5H, the address lines A7- A0 should have the following logic:
A7 A6 A5 A4 A3 A2 A1 AO
1 1 1 1 0 1 0 1 =F5H
The A2, A1 and A0 as input lines to the decoder. A3 can be connected to active low enable El5 and the remaining address lines can be con¬nected to E2 through the 4-input NAND gate. Figure shows an output port with the address F5H. The output 05 of the decoder is logically ANDed with the control signal IOW using the NOR gate (74LS02). The output of the NOR gate is the I/O select pulse that is used to enable the latch (74LS373). Logi¬cally ANDing IO/M and WR signals in the negative NAND gate IOW generate the control signal. The following programs are required to display digit 7 at the output port:

MVI A,78H ;Load seven-segment code in' the accumulator

OUT F5H ;Display digit 7 at port F5H
HLT ;End

Interfacing Input Devices:
(ii) Data Input from DIP Switches:
The circuit includes the 74LS138 3-to-8 decoder to decode the low-order bus and the tri-state octal buffer (74LS244) to interface the switches to the data bus.

Hardware:

Fig 3.2: 74LS244 tri-state octal buffer used as an interfacing

INTERFACING DIP SWITCHES.
The device has two groups of four buffers and they are controlled by the active low signals OE. When OE is high, the output lines are in the high impedance state.
Interfacing Circuit:
The figure shows that the low-order address bus, except A4 and A3, is connected to the decoder , the address lines A4 and A3 are left in the don't care state. The output line 04 of the decoder goes low when the address bus has the following ad¬dress ,

The control signal I/O Read (IOR) is generated by AND ing the IO/M and RD in a negative NAND gate, and the I/O select pulse is generated by ANDing the output of the decoder and the control signal IOR. When the address is 84H and the control signal IOR is asserted, the I/O select pulse enables the tri-state buffer and the logic levels of the switches are placed on the data bus. The 8085, then, begins to read switch positions during T3 and places the reading in the accumulator. When a switch is closed, it has logic 0, and when it is open, it is tied to +5 V, representing logic 1. Figure shows that the switches S7-S3 are open and S2-S0 are closed; thus, the in¬put reading will be F8H.


3.5 INPUT/OUTPUT PORTS :


Fig : 3.3 port connected with I/O Devices

The figure 3.3 shows the I/O ports. The 8255 programmable peripheral device, it has 3 ports , which are port A,B and C .,each port size is 8-bit , which can be used as I/O ports. . The I/O port consists essentially of several lines for data transfer and a few control lines. The ports can be used as I/O ports.
The simplest nonprogrammable 8-bit I/O port has 8 input and 8 output data lines. The input data is latched using the device select signal. The outputs are buffered and are tri-stated when the port is not selected.
Programmable I/O port s are programmed using I/O instructions like IN and OUT, which are the bidirectional port. By sending a Suitable command words ports will be selected in the 8255 chip.

Interfacing I/Os Using Decoders:



Figure: 3.4 Decode Logic for a Dip-Switch Input Port
In the Figures 8-input NAND gate used for address decoding , this technique has the disadvantage of having multiple addresses for the same device. In this circuit, a 3-to-8 decoder and a 4-input NAND gate are used to decode the address bus; the decoding of the address bus is the first step in interfacing I/O devices.
The address lines A2, A1, and A0 are used as input to the decoder, and the remaining address lines A7-A3 are used to en¬able the decoder. The address line A7 is directly connected to E3 (active high Enable line), and the address lines A6-A3 are connected to E1 and E2 (active low Enable lines) using the NAND gate.
The decoder has eight output lines; thus, we can use this circuit to gen¬erate eight device address pulses for eight different addresses.

(Figure: 3.5 address decoding using 3–8 decoder.)
The second step is to combine the decoded address with an appropriate control sig¬nal to generate the I/O select pulse. Figure shows that the output O0 of the decoder is logically AND ed in' a negative AND gate with the IOW control signal. The output of the gate is the I/O select pulse for an output port. The third step is to use this pulse to enable the output port. Figure shows that the I/O select pulse enables the LED latch with the output port address F8H, as shown below (A7-A0- is the demultiplexed low-order bus).

Address Decoding Using a 3-to-8 Decoder

Similarly, the output 02 of the decoder is combined with the I/O Read (IOR), signal, and the I/O select pulse is used to enable the input buffer with the address FAH.

Address Decoding Using a 3-to-8 Decoder



3.6 8259A-Programmable Interrupt Controller
The 8259A is a programmable interrupt controller. The following are the features of 8259A:
1. Handles up to 8-vectored priority interrupts.
2. It is cascadable for up to 64-vectored priority interrupts without additional circuiting.
3. The priority modes can be changed.
4. 8259A can be used with 8080/8085 or 8086/8088 Microprocessors.
5. The various interrupt modes it can operate are:
• Fully nested mode
• Rotating priority mode
• Special mask mode
• Polled mode.
6. 8259A supports both edge & level triggered mode of interrupting.
7. The data bus can be buffered.
8. The CALL address interval can be programmed to either 4 or 8
Pin Configuration Of 8259A
The fig 3.6 shows the pin out of 8259A.It has 28 pins using NMOS technology and requires a +5 V supply. The pin configuration of 8259A is illustrated in Fig D0-D7 Bidirectional data bus is used to transfer control, status and interrupt vector information.













FIG 3.6 8259A Pin Configuration.
CS (chip select)
When CS is low, enables 8259A to release status information onto the data bus for the CPU.
IR0-IR7 (Interrupt Request)
There are 8 interrupt lines from the devices. IRO having the highest priority and IR7 the lowest. The interrupt request is executed by raising an IR input (low to high) and holding it high until it is acknowledged (edge triggered mode), or just by a high level on an IR input (level triggered mode).
INTA (Interrupt Acknowledge)
The CPU issues this signal in response to an interrupt request by the 8259A. This signal is used by the 8259A to place the interrupt-vector type on the data bus so that the CPU can use it.
INT (Interrupt)
This pin goes high whenever a valid interrupt request is asserted. It is used to interrupt the CPU. Therefore it is connected to the CPU's interrupt pin.
CAS0-CAS2 (CASCADE LINES)
The CAS lines form a private 8259A bus to control a multiple 8259A structure. These pins perform as output from a master 8259A and inputs to a slave 8259A.
SP/EN (Slave Program/Enable Buffer)
This is a dual function pin. When in the buffered mode it can be used as an Output to control buffer transceivers (EN). When not in the buffered mode it is used as an input to designate a master (SP = 1) or a slave (SP = 0).

3.6 BLOCK DIAGRAM OF PROGRAMMABLE INTERRUPT CONTROLLER-8259A
The internal block diagram of 8259A is shown in Fig. 3.7 8259A has 8 blocks, they are:
1. Data Bus Buffer
2. Cascade Buffer/Comparator
3. Control Logic
4. Interrupt Request Register (IRR)
5. Priority Resolver (PR)
6. Interrupt Mask Register (IMR)
7. Interrupt Service Register (ISR)


FIG.3.7 Block Diagram of 8259.

Data Bus Buffer
This 3-state, bidirectional 8-bit data buffer is used to interface the 8259A to the system data bus. Control words and status information are transferred through the data bus buffer.
Read/Write Logic
This block receives the command from the CPU. It contains the initialization command word (ICW) register and the operation command word (OCW) register, which store the various control formats which define the device operation. This function block also allows the status of the 8359A to be transferred onto the data bus.
Cascade Buffer/Comparator
This function block stores and compares the ID (Identification Code) of all the 8259A's used in the system. The associated 3 I/O pins (CAS0-CAS2) are outputs when the 8259A is used as a master and are inputs when the 8259A is used as a slave. As a master, the 8259A sends the ID of the interrupting slave device on to the CAS0-CAS2 lines.
Control Logic
This logic block controls the overall operation of the controller. It generates interrupt to the microprocessor and receive INTA signal. It enables the data bus buffer to send the required information when INTA signal is obtained.

Interrupt Request Register (IRR)
IRR is used to store all the interrupt levels, which are requesting service.
Priority Resolver (PR)
The logic block determines the priorities of the bits set in the IRR. The highest priority is selected and strobe into the corresponding bit of the ISR in response to the pulse.
Interrupt Mask Register (IMR)
The IMR stores the interrupt mask information (i.e., whether each interrupt has to be enabled/disabled).
Interrupt Service Register (ISR)
The ISR is used to store all the interrupt levels, which are being serviced.

INTERRUPT SEQUENCE
1. One or more of the interrupt request lines (IRo-IR7) are raised high, setting the corresponding IRR bits.
2. The 8259A checks whether the mask register evaluates the highest priority and sends an INT (interrupt) signal to the CPU, if appropriate.
3. The CPU acknowledges the INT and responds with a INTA pulse after completing the execution of the instruction in process.
4. Upon receiving an ACK from the CPU, the highest priority ISR bit is set and the corresponding IRR bit is reset. The 8259A releases an 8-bit operational code CALL (CD) onto the data bus, which is read by the CPU.
5. The CPU after reading the CALL code (CD), understands that it has to send two more interrupt acknowledge to receive the CALL address.
6. During the second INTA signal becoming low, the 8259A sends the lower order 8 bits of the address.
7. During the third INTA signal becoming low, the 8259A sends the higher order 8-bits of the address.
8. In the AEOI mode the ISR bit is reset at the end of the second INTA pulse. Otherwise, the ISR bit remains set until an appropriate EOI command is issued at the end of the interrupt subroutine.


PROGRAMMING THE 8259A
The 8259A accepts two types of command words, as generated by the CPU. They are:
1. The Initialization Command Words (ICWs).
2. The Operation Command Words (OCWs).

Initialization Command Word 1 (ICW1)
Whenever a command is received with A0 = 0 and D4 = 1, this is interpreted by 8259A as an initialization sequence during which the following events automatically occur.
(i) The edge sense circuit is reset, which means that following the initialization, an interrupt request (IR) input must make a low-to-high transition to generate an interrupt,
(i) The interrupt mask register is cleared,
(ii) IR7 input is assigned priority 7.
(iv) The slave mode address is set to 7.
(v) The special mask mode is cleared and status read is set to IRR.
(vi) If D0-bit of ICWl (Fig. 3.8) is 0, then all functions selected in ICW4 are set to zero.

FIG 3.8 ICW1.


3.7 Block Diagram Of 8257(DMA –CONTROLLER):
The Figure 3.9 shows the block diagram of 8257. The 8257 block diagram has the following blocks:
1. Data Bus Buffer
2. Read/Write Logic
3. Control Logic and Mode Set Register
4. DMA Channels






Fig: 3.9 Block diagram of 8257
Data Bus Buffer
This three-state bi-directional, 8-bit buffer interfaces the 8257 to the system data bus. When the 8257 is being programmed by the CPU, eight bits of data for a DMA address register, a terminal count register, or the mode set register are received on the data bus. When the CPU reads the DMA address register, a terminal count, or the status register, the data is sent to the CPU over the data bus.
Read/Write Logic
When the CPU is programming or reading one of the 8257's registers (when 8257 is a slave device on the system bus), the read/write logic accepts the (I/OR) or (I/OW) signals and decodes the least significant four address bits, (A0-A3).
During DMA cycle the read/write logic generates the I/O read and memory write or I/O write and memory read signals which controls the data link with the peripheral that has been granted DMA cycle.
The different signals from the block are:
I/OR (I/O Read): It is active low bi-directional three-state line. In the slave mode, it is an input, which allows the 8-bit status register or upper/lower byte of a 16-bit DMA address register or terminal count register to be read. In the master mode, I/OR is a control output, which is used to access data from a peripheral during the DMA write cycle.
I/OW (I/O Write):
It is an active low bi-directional three-state line. In slave mode, it is an input, which allows microprocessor to write. In the master mode, I/OW is a control output, which allows data to be output in the peripheral during DMA read cycle.
CLK (Clock Input):
This clock will be the clock output of the microprocessor. The complete operation depends on the cycle speed.
RESET: It is an asynchronous input. It disables all DMA channels by clearing the mode register and tri-states all control lines.
A0-A3 (Address Lines): These least significant four address lines are bi-directional. In the "slave" mode they are inputs, which select one of the registers to be read or programmed. In the 'master' mode, they are outputs, which constitute the most significant 4 bits of the 16-bit memory address generated in the 8257.
CS (Chip Select): It is an active low input, which enables the I/O, read or I/O write input when the 8257 is being read or programmed in the "slave" mode. In the master mode, CS is automatically disabled to prevent the chip from selecting while performing the DMA function.
Control Logic Block
This block controls contents of the sequence of operations during all DMA cycles by generating the appropriate control signals and 16-bit address that specifies the memory relations to be accessed.
A4-A7 (Address Lines): These four address lines are tri-stated outputs which contains 4 to 7 of the 16-bit memory address generated by the 8257 during all DMA cycles.
READY: This asynchronous input is used to elongate the memory or I/O read and write cycles in the 8257 with wait states if the selected memory requires longer cycles. Wait states are included between S3 and S4 states of the duty transfer.
HRQ (Hold Request): This output requests control of the system bus. HRQ will normally be applied to the HOLD input on the CPU.
HLDA (Hold Acknowledge): This signal from the CPU to 8257 indicates that the 8257 have acquired control of the system bus. HLDA must remain stable during the specified set-up time.
MEMR (Memory Read): This active low three-state output is used to add data from the addressed memory location during DMA read cycles.
MEMW (Memory Write): This active low three-state output is used to write data into the addressed memory location during DMA write cycles.
ADSTB (Addressed Strobe): This output strobes the most significant byte of the memory address into the latch device from the data bus.
AEN (Address Enable): This output is used to disable the system data bus and system control bus. It may also be used to disable the system address bus by use of an enable on the address bus drivers in systems to inhibit non-DMA device from responding during DMA cycles
TC (Terminal Count): This output notifies the currently selected peripheral that the present DMA cycle should be the last cycle for this data block. If the TC stop bit in the Mode Set register in set, the selected channel will be automatically disabled at the end of that DMA cycle. TC is activated when the 14-bit value in the selected channel's terminal count register equals zero. The lower order 14-bit of the terminal count register should be loaded with the values (n-1) where n = the desired number of the DMA cycle.
MARK : This output notifies the selected peripheral that the current DMA cycle is the 128th cycle since the previous MARK output. MARK always occurs at 128 (and all multiples of 128) cycles from the end of the data block provided the count loaded is a multiple of 128.
DMA Channels
The 8257 provides 4 separate DMA channels each channel includes two 16-bit registers. (1) a DMA Address Register; (2) Initialized Count Register.
Both the registers must be initialized before a channel is enabled. The DMA address register is loaded with the address of the first memory location to be accessed. The value loaded into the low order 14 bits of the terminal count register specifies the number of DMA cycles minus one before the terminal count output is activated.
DRQ0-DRQ3 (DMA Request): These are individual asynchronous channel request inputs used by the peripherals to obtain a DMA cycle. If not in the rotating priority mode this DRQ0 has the highest priority and DRQ3 has the lowest. Raising the request line can generate a request and holding it high until DMA is acknowledged. For multiple DMA cycles (Burst Mode) the request line is held high until the DMA acknowledge of the last cycle arrives.
DACK0 - DACK3 (DMA Acknowledged): An active low level on the acknowledge output informs the peripheral connected to that channel that it has been selected for a DMA cycle. The DACK output acts as a chip select for the peripheral device requesting service. This line goes active (low) and inactive (high), once for each byte (transferred) even if a burst of data is being transferred.

MODE SET REGISTER (MSR)
The CPU normally programs the mode set register after the DMA address register(s) and terminal count register(s) are initialized. The MSR is cleared by RESET input, thus disabling all options, inhibiting all channels and preventing bus conflicts on power-up. A channel should not be left enabled unless its DMA address and terminal count registers contain valid values; otherwise, an inadvertent DMA request from a peripheral could initiate a DMA cycle that would destroy memory data.

Fig 3.10 Mode Set Register
Rotating Priority
By setting the bit 4 of the mode set register of 8257 , rotating priority can be set. In the rotating priority mode the priority of the channels has a circular sequence. It is shown in Fig. 3.10. After each DMA cycle, the priority of each channel changes. The channel, which had just been serviced, will have a lowest priority. If the rotating priority bit is reset , each DMA channel has a fixed priority in the fixed priority mode.
Extended Write
If this bit is set, the duration of both the MEMW and IOW signals activating them earlier in the DMA cycle. Instead of these two signals being, middle of S3 state, the 8257 will make it low during the beginning of S3 the devices to be ready for the data transfer.
TC Stop
If the TC stop bit is set, a channel is disabled (i.e., its enable bit is reset) of count output goes true, thus preventing automatically DMA operation c If the TC stop bit is not set, the occurrence of the TC output has no effect enables bits.
Auto Load
The auto load mode permits channel-2 to be used for repeat block or t operations without immediate software intervention between blocks. Note that the TC stop feature has no effect on channel-2 when the load bit is set.
Status Register
Figure 3.11 shows the status register of 8257.


Fig:3.11 Status register of 8257
Update FLAG is cleared either by resetting the 8257, by changing to the non-auto load mode or it can be left to clear itself at the completion of the update cycle. The purpose of the update FLAG is t prevent the CPU from inadvertently stopping a data block by overwriting a starting address or terminal count in the channel-3 register before these parameters are properly auto-load into channel-2.

3.9 lntel – 8251 UNIVERSAL SYNCHRONOUS ASYNCHRONOUS RECEIVER AND TRANSMITTER (USART)
The figure 3.12 shows the USART. It is a Programmable Serial Communication Interface Chip, designed for both, synchronous and asynchronous, serial data transfer. It is packed in a 28 pin DIP.
The block diagram has 5 (five) section:
(1) Read/Write Control logic,
(2) Transmitter,
(3) Receiver,
(4) Data Bus Buffer and
(5) Modem Control.
The Read/Write control logic interfaces 8251A with CPU determines the functions of 8251 A, according to the control word written into its control-register and monitors the data flow.
The signals RD, WR and CS are used for read/write operations with the three registers (control, status and data buffer registers). When C/D is HIGH, the control-register is selected for writing control word or reading status-word. When C/D is LOW, the data buffer is selected for read/write operation. A HIGH on the reset input, forces the 8251A into idle-mode. Thus, units needs a clock-input also but this clock-signal does not control either the serial data-transfer or the reception-rate. The transmitter section accepts parallel data for CPU and converts them into serial data. This section is double-buffered, i.e., a buffer-register to hold 8-bit data, and another register (output register) to convert the previous data into a stream of serial bits.

FIG:3.12 Block diagram of USART
Receiver section accepts serial data, and converts it into parallel data. Like the transmitter section, it is also double-buffered. The modern control unit allows to interface a MODEM to 8251 A, out establish data communication through MODEM over telephone lines and also takes care of hand-shake signals for MODEM-interface. The control-words of 8251-A are MODE WORD and COMMAND WORD.

Dynamic RAM Refresh Using DMA:
Dynamic RAM interfacing involves the following tasks:
1. Multiplex row and column address bits to the address inputs of the DRAM chip.
2. . Generate RAS and CAS signals.
3. . Refresh the DRAM.

The use of a DRAM controller minimizes the IC part count and reduces the inherent complexity of DRAM interfacing. A PAL based interface de¬sign is useful when the controller is not compatible with the microprocessor being used and the size of the DRAMs is too large for the controller. For example, the Intel 8208 can directly drive only up to 256 K DRAMs.
A disadvantage of this system is no refreshment when the microprocessor stops executing instructions. No refresh occurs while the microprocessor is stopped. During a DMA transfer, such as when data is being transferred from the memory to an I/O device, sufficient refresh cycles may not occur thereby causing data in the DRAM to be lost.
Burst and Distributed Refresh
If 256 K bit DRAMs are being used, then we know that all the 256K need to be refreshed at least once every 4 ms. This can be done by executing the following operations:
1. Generate a refresh request once every 15 Micro second. This request can generated by a programmable timer such as the Intel 8254.
2. The refresh request forces a DMA controller to execute a DMA read cycle on the bus. One of the channels of the DMA controller can be programmed for operation in single cycle mode so that it places an address on the address bus and performs a read. The address space of the 8085 is small enough to justify the used SRAMs, instead of DRAMs.

3.10 Analog Input Devices:

8-BIT A/D CONVERTER:
Figure 3.13 (a) shows a schematic of interfacing a typical A/D converter using status check. The A/D converter has one Analog input signal is Converted in to digital signals. The analog signal can range from 0 to 10 V, or ±5 V. In addition, the converter shows two lines START and DR (Data Ready), both active low. When an active low pulse is sent to the START pin, the DA
FIGURE 3.13 (a) Interfacing an A/D Converter Using the Status Check

goes high and the output lines go into the high impedance state. The rising edge of the START pulse initiates the conversion. When the conversion is complete, the DR goes low, and the data are made available on the output lines that can be read by the micro-processor. To interface this converter, we need one output port to send a START pulse and two input ports: one to check the status of the DR line and the other to read the out¬put of the converter.
In Figure , the address decoding is performed by using the 3-to-8 decoder (74LS138), the 4-input NAND gate, and inverters. Three output lines of the decoder are combined with appropriate control signals (IOW and IOR) to assign three port ad¬dresses from 80H to 82H. The output port 82H is used to send a START pulse by writ¬ing the OUT instruction; in this case, we are interested in getting a pulse from the micro¬processor, and the contents of the accumulator are irrelevant to start the conversion.
However, for some converters the IOW pulse from the microprocessor may not be long enough to start the conversion. When the conversion begins, the DR (Data Ready) goes high and stays high until the conversion is completed.
The status of the DR line is moni¬tored by connecting the line to bit D0 of the data bus through a tri-state buffer with the in¬put port address 80H. The processor will continue to read port 80H until bit D0 goes low. When the DR goes active, the data are available on the output lines of the converter, and the processor can access that data by reading the input port 81H. The subroutine instruc¬tions, to initiate the conversion and to read output data, and the flowchart are shown in Figure.3.14


Figure: 3.14 flowchart of A/D conversion process3.11ANALOG OUT PUT DEVICE: 8- Bit D/A converter:

Figure: 3.11.1 D/A converter using IC 1408
The figure 3.15 shows the 8 bit D/A converter. Which includes an 8-input NAND gate and a NOR gate (negative AND) as the address decoding logic, the 74LS373 as a latch, and an industry-standard 1408 D/A converter. The address lines A7-A0 are decoded using the 8-input NAND gate, and the output of the NAND gate is combined with the control signal IOW. When the microprocessor sends the address FFH, the output of the negative AND gate en¬ables the latch, and the data bits are placed on the input lines of the converter for conver¬sion.
The 1408 is an 8-bit D/A converter compatible with TTL and. CMOS logic, with the settling time around 300 ns. It has eight input data lines A1 (MSB) through A8 (LSB). It requires 2 mA reference current for full-scale input and two power supplies Vcc = +5 V and VEE = -15 V .

where inputs A1 through A8 = 0 or 1.
This formula is an application of the generalized formula for the current Io. For full-scale input (D7 through D0 = 1),

The total reference current source is determined by the resistor R14 and the voltage VRef. The resistor R15 is generally equal to Rl4 to match the input impedance of the ref¬erence source. The output I0 is calculated as follows:
The output is 1 LSB less than the full-scale reference source of 2 mA. The output voltage V0 for the full-scale input is
V0 = 2 mA (255/256) x 5 k = 9.961 V
PROGRAM: for continuous waveform,

This program outputs 00 to FF continuously to the D/A con¬verter. The analog output of the DAC starts at 0 and increases up to 10 V as a ramp.


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Responses to " Interfacing devices and phripheral devices :-"
Guest Author: Nambiar S     15 Jan 2013
Interfacing devices used in system with various peripheral is very informative, good wokr


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