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Introduction to Intel 8085:-
Posted Date: 03 Feb 2008 Resource Type: Articles/Knowledge Sharing Category: Computer & Technology
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Posted By: prakash Member Level: Silver
Rating:  Points: 5
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MICROPROCESSOR AND APPLICATIONS - 06PCA07
UNIT II:
2.1 INTRODUCION OF MICROPROCESSOR:
Fig : 2.0 Block diagram of Microprocessor
The figure 2.0 shows the block diagram of Microprocessor. The microprocessor is a semiconductor device, which has electronic logic circuits. It is also called as CPU. Which is made of very-large-scale integration (VLSI) technique. The microprocessor can perform various com¬puting functions and making decisions.
Microprocessor can be divided into three blocks,
1. Arithmetic/logic unit (ALU).
2. Register unit.
3. Control unit.
Arithmetic/Logic Unit
The ALU unit performs such arithmetic operations as addition and subtraction, and such logic operations as AND, OR, and exclusive OR.
Register unit
The microprocessor consists of various registers such as B, C, D, E, H, and L. These registers are primarily used to store data temporarily during the execution of a program.
Control Unit
The control unit provides the necessary timing and control signals to all the operations in the microprocessor. It controls the flow of data between the micro¬processor and memory and peripherals.
2.2 REGISTER SET OF 8085:
Fig : 2.1 8085 Register set
ACCUMULATOR
The accumulator is an 8-bit register that is part of the arithmetic/logic unit (ALU). This register is used to store 8-bit data and to perform arithmetic and logical operations. The result is stored in the accumulator. The accumulator is also called register A.
REGISTERS:
The 8085 has six general-purpose registers, the registers are B, C, D, E, H, and L, as shown in Figure 2.1. Each register can store 8-bit data. These registers can be combined as register pairs BC, DE, and HL, Which can perform 16-bit operations.
These registers are programmable, meaning that a programmer can use them to load or copy data from the registers by using instructions. For example, the instruction MOV A, C copies the data from register C to register A.
FLAG REGISTER:
Fig 2.2 Flag register of 8085
Figure 2.2 shows an 8-bit flag register. The flags are affected by arithmetic and logic operations in the ALU, and the result is always stored in the accumulator.
The 8085 microprocessor has 5 flags,
1. Zero flag: The zero flag is set, when the ALU operation results a zero .
2. Carry flag: If an arithmetic operations results in a carry, this flag is set.
3. Parity flag: This flag is set, when an arithmetic or logical operation results in a data, which has even number of 1s. If otherwise, it is reset.
4. Sign flag: After the execution of an arithmetic or logic operations, if D7 bit of the accumulator is 1, it indicates a negative number and this flag is set. If otherwise, it is reset.
5. Auxiliary Carry flag: used for BCD Operations, During the BCD operations, if D3 bit producing the carry then the AC bit set as1, otherwise the bit is 0.
6. Carry Flag: when a carry is generated by digit D7, then the carry flag set as 1, otherwise the bit will be 0.
PROGRAM COUNTER (PC)
The program counter is a 16-bit register. It is also called as memory pointer. Memory locations have 16-bit addresses. The function of the program counter is to point to the memory address of the next instruction to be fetched. When a byte is fetched, the program counter is incremented by one and which points the next memory address in the memory.
STACK POINTER (SP)
The stack pointer is also a 16-bit register, used as a memory pointer. It points to a memory lo¬cation in R/W memory, called the stack. The beginning of the stack is defined by loading a 16-bit address in the stack pointer.
2.3 Memory addressing:
The memory address range of IK (1024 x 8) memory shown in Figure 2.3.
Fig 2.3 Memory Address Range: 1024 Bytes of Memory
The memory (RAM)chip has 1024 registers, therefore 10 address lines (A9-Ao) are required to address these registers. The remaining six address lines (A15- A10) of the microprocessor are used for the Chip Select (CS) signal. In Figure the memory chip is enabled when the address lines A15-AA10 are at logic 0. The address lines A9- A0 can address 1024 registers, starting from all 0’s to all 1’s. If Al5 is connected to the NAND gate without an inverter, the memory addresses will range from 8000H to 83FFH.
2.4 Addressing modes:
The data are specified in different modes in the instructions. The various ways of specifying data are called addressing modes.
The 8085 microprocessor has 5 types of addressing modes
1. Immediate Addressing mode
2. Register Addressing mode
3. Direct Addressing mode
4. Indirect Addressing mode
5. Implied Addressing mode
1. Immediate Addressing mode :
When the data is directly specified in the instruction, Which is called immediate addressing mode.( MVI reg, Data)
Example:
MVI B, 72H
LXI H,5000H
2. Register Addressing mode:
When the data is stored in the register and if the register is specified in the instruction, then it is called register addressing mode . ( MOV Rd., Rs).
Eg: MOV D, C;
The contents of C is moved to register D.
3. Direct Addressing mode:
When the memory Address specified with in the instruction, then it is called direct addressing mode.
Eg: LDA 5000H;
The 5000H memory content is stored in to the accumulator.
4.Indirect Addressing mode:
Load the data , to the accumulator from the memory. The data which is pointed by the memory pointer(HL reg),it is called indirect addressing mode.
Example:
MOV A, M
The data moved to accumulator from the memory, which is pointed by the memory pointer.
5. Implied Addressing mode:
When the instruction itself specifies the data to be operated, then it is called
Implied addressing mode.
Example:
CMA - Complement the content of accumulator.
RRC- rotate accumulator content with out carry.
2.6 TIMING METHODS:
The microprocessor is required to provide time delays for ON/OFF devices such as pumps or motors.
DELAY: DCX D ; Decrement the D,E contents,
MOV A, D ;The D content copied to A.
ORA E ; Are the contents zero?
JNZ DELAY
RET
Time Delay can be calculated in the following methods,
Instruction Number of Cycles
CALL 18
DCX D 6
MOVA.D 4
ORA E 4
JNZ 7/10
RET 10
Cycles for DCX D + cycles for MOV A, D + cycles for ORA E + cycles for JNZ
6 + 4 + 4+ 10 = 24 cycles this 24 cycles will be performed (y — 1) times. Where y is the initial contents of D,E. For the final iteration in which no jump is performed and the JNZ condition is not satisfied (Z =£ 0), the number of cycles is equal to cycles for DCX D -1- cycles for MOV A, D + cycles for ORA E + cycles for JNZ + cycles for RET = 6 + 4 + 4 + 7+ 10 = 31 cycles
Therefore, the time used, including a CALL instruc¬tion, is
18 + 31 + 24(y - 1) = 49 + 24(y - 1) clock cycles
Suppose that in a program a delay time of 1/3 ms is desired. The DELAY routine can be used to accomplish this in the following way. Each cycle of the 8085 clock is 1/3 ?s (3 MHz). The number of cycles required in the DELAY routine is
1/3 ms/1/3?s = 1000 cycles
Therefore, the initial counter value y of the D,E register pair can be calculated as follows:
49 + 24(y - 1) = 1000
24(y - 1) = 951
y =951/24+ 1 = 4010 = 28I6
Therefore, in the program the D,E register pair can be loaded with 002816 and the DELAY routine can be called to obtain 1/3 ms of time delay.
2.7 Pin Configuration and Associated Signals of 8085 Microprocessor:
The figure shows the pin out of 8085 microprocessor. It is a 8-bit microprocessor, which can address 64K of memory. 8085 microprocessor has 40 pins and requires a +5V power supply and can operate with a 3 MHz single-phase clock. Each pin has an input or output signal. These signals are classified as follows.
1. Address Bus
2. Data Bus
3. Control & Status signal.
4. Power supply and frequency signals
5. Externally initiated signals
6. Serial I/O ports
Fig. 2.4 8085 Pin Configuration
ADDRESS BUS
The 8085 microprocessor has a 16 bit address lines (A15-A0), These are the unidirectional bus, the address buses are divided in to two groups, higher order bus ((A15-A8)and lower ordered bus(A7-A0). The lower order address bus AD7-AD0 are called as multiplexed bus. The lower ordered bus can carry the address and data.
DATA BUS
The 8085 microprocessor has a 8bit data lines (A7-A0), The data lines AD7 - AD0 are bidirectional and are multiplexed. These buses can carry address and data, the address transfer and the data transfer is controlled by the control signal ALE.
CONTROL & STATUS SIGNAL
The group of signals includes two control signals (RD and WR), three status signals (IO/M, S1 and S0) to identify the operation, and a special signal (ALE), to select the mode of multiplexed bus.
RD: Read control signal is an active low signal. Which indicates that the microprocessor connected to I/O or memory device has to read the data available in the data bus.
WR: Write control signal is an active low signal. which indicates that the data on the data bus are to be written in the selected I/O or memory device.
10/M: This status signals indicates whether the operation is with I/O devices or memory when it is high, it indicates an I/O operation. When it is low, it indicates a memory operation.
S1 and So: These are status signals, to identify the operation such as opcode fetch, memory read, memory write, I/O read, I/O write, etc.
ALE :(Address Latch Enable) This is a positive pulse generated at the beginning of an operation. It indicates that AD7toADo are lower order address lines. This signal is used to enable the latch of the lower order address from the multiplexed bus.
POWER SUPPLY AND CLOCK FREQUENCY
Power supply signals are:
a. Vcc + 5V power supply
b. Vss Ground Reference.
Clock signals are
c. X1, X2: A crystal is connected at these two pins. Two internally divides the Frequency; therefore to operate a system at 3MHz, the crystal should have a frequency of 6MHz.
CLK: clock signal, which controls the whole operations of the microprocessor.
EXTERNALLY INITIATED SIGNALS
External initiated signals are 5 interrupt signals, RESET HOLD and READY signals.
• INTR This signal is active high signal, which is used to indicate the interrupt.
• INTA This signal is active low signal, which issued to acknowledge the interrupt.
• RST Restart Interrupt signal, which are vectored interrupts that transfer the
program control to specific memory location.
• TRAP This is a non-maskable interrupt and has the highest priority.
• HOLD This signal indicates that a peripheral such as a DMA controllers is requesting to use the address and data bus.
• HLDA This is an acknowledge signal for the HOLD request signal given by the microprocessor.
• READY This signal is used to delay the microprocessor read or write cycles until a
slow responding peripheral is ready to send or accept data.
• RESET IN When the signal on this pin goes low, the program counter is set to zero, the
MPU is reset.
• RESET OUT This signal indicates that the MPU is being reset.
SERIAL I/O PORTS
The 8085 has two signals to perform the serial transmission through SID and SOD.
(Serial input data and serial output data).
2.8 8085 Instruction Timing and Execution:
INPUT-OUTPUT (I/O) READ MACHINE CYCLE:
Fig: 2.5 Timing diagram of I/O Read Machine Cycle
Fig 2.5 shows the timing diagram of I/O Read machine cycle. The I/O Read Machine cycle is executed by the microprocessor to read a data from an input device. It consists of 3T states. The IN Instruction uses this machine cycle during the execution.
INPUT - OUTPUT (I/O) WRITE MACHINE CYCLE
Fig: 2.6 Timing diagram of I/O write machine cycle
Fig. 2.6 shows the timing diagram of I/O Write Machine cycle. The I/O write machine cycle is executed by the microprocessor to write a data byte from an output device. It consists of 3T states. The instruction, which sends the data to the output device, comes under this machine cycle.
Instruction cycle is defined, as the time required completing the execution of an instruction.
An Instruction Cycle will have one to six machine cycles.
2.9 8085 PROGRAMMED I/O:
There are two I/O instructions are used in the 8085, Which are IN and OUT. These instructions are 2 bytes long. The first byte defines the OP code of the instruction, and the second byte specifies the I/O port number. Execution of the IN PORT instruction causes the 8085 to receive 1 byte of data into the accumulator from a specified I/O port. On the other hand, the OUT PORT instruction, when executed, causes the 8085 to send 1 byte of data from the accumulator into a specified I/O port.
The 8085 can access I/O ports using standard I/O or memory-mapped I/O.In standard I/O, the 8085 inputs or outputs data using IN or OUT instructions. Each of these instructions re¬quires 2 bytes. The first byte contains the OP code fol¬lowed by the second byte defining the I/O port number. The IN PORT instruction loads a byte into the accu¬mulator from an I/O port defined in the instruction. The OUT PORT outputs a byte from the accumulator into an I/O port specified in the instruction.
In memory-mapped I/O, the 8085 maps I/O ports as memory addresses. Hence, LDA addr or STA addr in¬structions are used to input or output data to or from the 8085. The 8085's programmed I/O capabilities are ob¬tained via the support chips, namely, the 8355/8755 and 8155/8156. As mentioned before, the 8355/8755 contains a 2K byte ROM/EPROM and two 8-bit I/O port A and B.
The 8155/8156 contains a 256-byte RAM, bit and one 6-bit I/O ports, and a 16-bit programmable timer. The only difference between the 8155 is that chip enable is LOW on the 8155 and it i on the 8156. We now describe the I/O ports as; with 8355/8755 and 8155/8156 in the following, graphs.
2.10 Interrupt System:
Interrupt is an event (task), which will ignore some special operations through the software.
Types of Interrupts:
Interrupts are two types
(1)| Software
(2) Hardware.
The software interrupts are program-instructions, which are inserted at desired locations in a program. An external device initiates the hardware interrupts
interrupts are classified as
(1) Vectored
(2) Non-vectored
In vectored-interrupts the microprocessor automatically goes to a specific address, and give response to the interrupt-request.
In non-vectored interrupt, the interrupted device has to give the address of the interrupt-service-routine.
The first four of the interrupts are allotted memory-locations where the programs corresponding to that interrupt-service-sub-routine (ISS) are stored. The I/O devices have to be entered in the memory locations given in Table
The 8085 microprocessor has maskable interrupts RST 7.5, RST 6.5 and RST 5.5. Masking is done by carrying out a instruction called Set Interrupt Mask (SIM). To find out whether any of these interrupt has been masked-off and to clear-off the mask, we make use of another instruction called as Read Interrupt Mask (RIM). In 8085 microprocessor , TRAP interrupt is non-masked interrupt, and which is the highest priority interrupt.
8085 DMA:( Direct memory access)
Fig : 2.7 8085 Interfaced with 8257
The fig 2.7 shows DMA interfacing. The Intel 8257 DMA has 40-pins and it is also programmable. It is compatible with the 8085 micro¬processor. The 8257 is a four-channel DMA controller with priority logic built into the chip. This means that the 8257 provides for DMA transfers for a maximum of four devices via the DMA request lines DRQ0-DRQ3 (DRQo has the highest priority and DRQ3 the low¬est). Associated with each DRQ is a DMA acknowledge line(DACKo-DACK3 for the four DMA requests DRQ0- DRQ3). Note that the DACK signals are active LOW. The 8257 uses the 8085 HOLD pin in order to take over the system bus. After initializing the 8257 by the 8085, the 8257 perform the DMA operation in order to transfer a block of data of up to 16,384 bytes between the memory and a peripheral without involving the microprocessor. A typical 8085-8257 interface is shown in Figure. An I/O device can request for a DMA transfer by raising the DMA request (DRQ) line of one of the chan¬nels of the 8257. In response, the 8257 will send a HOLD request (HRQ) to the 8085. The 8257 waits for the HOLD acknowledge (HLDA) from the 8085. On receipt of the HLDA from the 8085, the 8257 generate a LOW on the DACK lines for the I/O device. Note that the DACK is used as a chip select bit for the I/O device. The 8257 sends the READ or WRITE control signals, and an 8-bit data is transferred between the I/O and memory. On completion of the data transfer, the DACK is set to HIGH, and the HRQ line is reset to LOW in order to transfer control of the bus to the 8085. The 8257 utilizes four clock cycles in order to transfer 8 bits of data.
The 8257 has three main registers. These are a 16-bit DMA address register, a terminal count register, and a status register. Both address and terminal count registers must be initialized before a DMA operation. The DMA address register is initialized with the starting address of the memory to be written into or read from. The low-order 14 bits of the terminal count register are initialized with the value (n — 1), where n is the desired number of DMA cycles. A terminal count (TC) pin on the 8257 is set to HIGH in order to indicate to the peripheral device that the present DMA cycle is the last cycle. An 8-bit status register in the 8257 is used to indicate which chan¬nels have attained a terminal count.
1.12 8085 SID and SOD lines:
Serial I/O is used for data transfer between a peripheral device and microprocessor. Since mi¬croprocessors perform internal operations in parallel, conversion of data from parallel to serial is required to provide communication between the mi¬croprocessor and the serial I/O. The 8085 provides serial I/O capabilities via SID (serial input data) and SOD (serial output data) lines.
One can transfer data to or from the SID or SOD lines using the instructions RIM and SIM . After executing the RIM instruction, the bits in the ac¬cumulator are interpreted as follows:
1. Serial input bit is bit 7 of the accumulator.
2. Bits 0-6 are interrupt masks, the interrupt enable bit, and pending interrupts.
The SIM instruction sends the contents of the accumulator to the interrupt mask register and serial output line. There¬fore, before executing the SIM, the accumulator must be loaded with proper data. The contents of the accumulator are interpreted as follows:
1. Bit 7 of the accumulator is the serial output bit.
2. The SOD enable bit is bit 6 of the accumulator. This bit must be 1 in order to output bit 7 of the accu¬mulator to the SOD line.
3. Bits 0-5 are interrupt masks, enables, and resets.
2.13 8085-BASED SYSTEM DESIGN
Fig : 2.8 8085 Based System Design
The fig 2.8 shows the 8085 microprocessor based system design. The microprocessor can control the I/O devices or systems with the help of assembly language programs.
A microcomputer with a 2K EPROM (2716), a 256-byte RAM, and three ports (8155) is de¬signed. An 8085 assembly language program is provided to multiply 4-bit numbers entered via DIP switches connected to port A. The 8-bit product is displayed on two seven-segment displays interfaced via port B. Repeated addition will be used for multiplication. Full decoding using the 74LS138 decoder is utilized..
Using an EPROM programmer, the program location starting at location 0000H, can program the 2716.The inputs are activated by the dipswitch LOW and HIGH.
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