Download Model question papers & previous years question papers
Submit Previous Years University Question Papers
Posted Date: 19 Jul 2008 Posted By:: Vidya Member Level: Gold Points: 5 (₹ 1)
2005 Janardan Rai Nagar Rajasthan Vidyapeeth M.Tech. Computer Science MSVD03-VERNILOG HARDWARE DESCRIPTION LANGUAGE University Question paper
MASTER OF TECHNOLOGY
(SEMESTER - IV )(ELECTRONICS TELECOMMUNICATION/COMPUTER)
(SPL-4:VLSI DEIGN & EMBEDDED SYSTEM)
MSVD03-VERNILOG HARDWARE DESCRIPTION LANGUAGE
TIME: 03 HOURS MAX. MARKS: 75
1. Question paper is divided into three groups
2. Each group is of 25 marks each
3. Figure to the right in bracket indicates mark
4. Assume suitable data if necessary
GROUP A: Answer any three questions. Question No. 1 is compulsory.
Q 1. Distingush between vernilog HDL and VHDL. (5)
Q 2. Enumerate and explain different modeling vernilog HDL. (10)
Q.3. What do you mean by operator? (10)
Q.4. Explain combinatorial UDP along with one example (10)
Q.5. Explain laxical conventions. (10)
GROUP B: Answer any three questions. Question No. 6 is compulsory.
Q 6. Explain design abstraction hierarchy. (5)
Q 7 Explain difference between synthesizable and behavioral modeling. (10)
Q 8. Explain parameterized modules along with one example. (10)
Q 9. Explain state machine types. (10)
Q.10. Enumerate and explain loop statement. (10)
GROUP C: All Questions are Compulsory.
Q.11 Fill in the blanks (each question carries 2 marks)
(i) ___________________ loop is executed as long as its condition is true.
(ii) Registers are unsigned ________________.
(iii) UDPS always have _________________ input.
(iv) Z mems _________________.
(v) String are stored in _________________.
Q.12 Multiple choice question. (Each question carries 2 marks)
(i) Memories are arrays of :
a. Flip – flop
(ii) Territory operation takes ____________________ operands.
(iii) For sequential VDP, f stands for :
i. Rising edge
j. Falling edge
k. Any change
(iv) Take contains ________________ statement.
(v) Function must take _________________ time.
Q.13 True or false (each question carries 1 mark).
(i) Integers are signed
(ii) Loops uses three expressions
(iii ) Function must return the value
(iv) Concentration can be used on one sides of an assignment
(v) The wait statement if it is condition is true.
Return to question paper search
and make money from adsense revenue sharing program
Are you preparing for a university examination? Download model question papers
and practise before you write the exam.