Rajiv Gandhi Proudyogiki Vishwavidyalaya(Technical University) VLSI model question papers



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Posted Date: 26 Jan 2010      Posted By:: Er. Akanksha Pandey    Member Level: Gold  Points: 5 (₹ 1)

2007 Rajiv Gandhi Proudyogiki Vishwavidyalaya(Technical University) B.E. Electronics and Instrumentation Engineering VLSI Question paper



Course: B.E. Electronics and Instrumentation Engineering   University/board: Rajiv Gandhi Proudyogiki Vishwavidyalaya(Technical University)





VLSI (EI-8401)

Note: Attempt five questions in all including no. 1 which is compulsory. Make suitable assumptions wherever necessary. Support your answers with suitable sketches.

1. (a) Give in short the answers of the following:

(i) What is Moore's law? [Marks 3]
(ii) Define sheet resistance. [Marks 3]
(iii) Define Interstitial Diffusion. [Marks 2]
(iv) What should be the value of the ratio Zp.u /Zp.d for an NMOS invertor driven through one or more pass transistors. [Marks 2]
(v) Why is the packing density of MOS transistors more than that of bipplar transistors ?
[Marks 3]
(vi) Write the advantages of ion implantation process over diffusion process. [Marks 4]

2. Define the following phenomena associated with MOS transistors: [Marks 20]

(i) Body effect
(ii) Mobility variation
(iii) Impact ionization
(iv) Channel length modulation

3. (a) Describe the process of fabrication of silicn gate NMOS transistor. Clearly illustrate the sequence of processes with proper diagram. [Marks 12]

(b) Draw the cross-section of a CMOS transistor showing the parasitic transistor and resistors resulting in latch-up problem. Briefly explain the cause of latch-up. [Marks 8]

4. (a) Draw the circuit diagram and stick diagram of the following: [Marks 10]

(i) Two input CMOS NOR gate
(ii) Three input NMOS NAND gate

(b) Draw the structure of a Twin Tub CMOS transistor. Write the relative merits of twin tub process over its other counterparts. [Marks 10]

5. (a) What do you mean by dynamic CMOS logic? Differentiate it from Domino CMOS logic. [Marks 10]
(b) Explain parity generator circuit with the help of structured design approach. [Marks 10]

6. (a) Illustrate the implementation of ALU functions with adders. [Marks 10]
(b) Explain in brief, a 4-bit serial parallel multiplier. [Marks 10]

7. (a) Draw and explain the NMOS invertor circuit with its characteristics. Make use of a depletion mode transistor as the load. [Marks 10]
(b) Explain resistance estimation and capacitance estimation n brief. [Marks 10]

8. Write short notes on any three of the following: [Marks 20]

(i) Czochralski process (CZ process)
(ii) Mead conway design rules
(iii) Dynamic shift registers
(iv) Modified Booth's algorithm
(v) Small signal A.C characteristics of MOS transistors.





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